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15592 Commits

Author SHA1 Message Date
Robert O'Callahan e906ea3f1b Add tests for dynamic precision and with with an int parameter 2025-08-15 23:58:58 +00:00
KrystalDelusion 4a324e1da8
Merge pull request #5292 from rocallahan/wasm-varargs 
Fix vararg alignment
 2025-08-16 10:29:36 +12:00
Emil J 70600bb596
Merge pull request #5239 from rocallahan/abc-incremental 
In the ABC pass, avoid scanning the entire module for each ABC run
 2025-08-15 20:17:32 +02:00
Robert O'Callahan 6d62a1fff7 Fix vararg alignment 2025-08-15 05:43:53 +00:00
github-actions[bot] bf625951d7 Bump version 2025-08-15 00:26:03 +00:00
Robert O'Callahan 62c441107d Build FfInitVals for the entire module once and use it for every ABC run. 2025-08-14 22:29:51 +00:00
Robert O'Callahan 2654bd5355 Compute `is_port` in AbcPass without iterating through all cells and wires in the module every time we run ABC. 
This does not scale when we run ABC thousands of times in a single AbcPass.
 2025-08-14 22:29:45 +00:00
Robert O'Callahan ac8259b02e Preserve `assign_map` across ABC invocations. 
Currently `assign_map` is rebuilt from the module from scratch every time we invoke ABC.
That doesn't scale when we do thousands of ABC runs over large modules. Instead,
create it once and then maintain incrementally it as we update the module.
 2025-08-14 22:27:04 +00:00
Robert O'Callahan 4de3ee093e Mark kept FF output wires as ports directly instead of via the 'keep' attribute 2025-08-14 22:26:38 +00:00
Emil J 195d3ef940
Merge pull request #5100 from jix/rename_move_to_cell 
rename: add -move-to-cell option in -wire mode
 2025-08-14 16:45:33 +02:00
Miodrag Milanovic 1dbf2df983 Add libfl-dev for CodeQL CI job 2025-08-14 09:15:43 +02:00
github-actions[bot] a265b23ac0 Bump version 2025-08-14 00:25:16 +00:00
Emil J dbb977aa8b
Merge pull request #5288 from YosysHQ/emil/demote-verilog-parser-errors-again 
verilog: demote some parser errors to warnings again
 2025-08-13 12:52:50 +02:00
Emil J. Tywoniak 856fc43a87 rename: format vector slices consistently with HDL upto/downto direction 2025-08-13 11:11:53 +02:00
Jannis Harder 77089a8d03 rename: add -move-to-cell option in -wire mode 2025-08-13 11:11:52 +02:00
Emil J. Tywoniak 1603828b30 verilog_parser: fix locations of warnings for restrict keyword 2025-08-13 10:56:48 +02:00
Emil J. Tywoniak 910ff3ff36 verilog: demote some parser errors to warnings again 2025-08-13 10:54:47 +02:00
Robert O'Callahan ccb23ffc1a Fix indentation 2025-08-13 05:44:52 +00:00
Robert O'Callahan 885bb744e3 Make `module` a parameter of the function so we can change its constness in context 2025-08-13 05:44:52 +00:00
Robert O'Callahan 53c72c0d39 Move code in `abc_module()` that modifies the design into a new function `extract()` 
Splits up the big `abc_module()` function and isolates the code that modifies the design
after running ABC.
 2025-08-13 05:44:52 +00:00
Robert O'Callahan ceedcecfae Move the input parameters to `abc_module` that are identical across modules to an `AbcConfig` struct. 2025-08-13 05:44:52 +00:00
Robert O'Callahan 4ba42c4752 Move ABC pass state to a struct instead of storing it in global variables. 2025-08-13 05:44:52 +00:00
github-actions[bot] 8634d83320 Bump version 2025-08-13 00:25:15 +00:00
Emil J 9d047f9a30
Merge pull request #5283 from YosysHQ/emil/fix-simplify-initstate 
simplify: fix initstate crash
 2025-08-12 14:28:31 +02:00
Emil J. Tywoniak 6042ae0e8a simplify: add smoke test for system function calls 2025-08-12 12:59:31 +02:00
Emil J. Tywoniak 8582136a45 simplify: fix $initstate segfault 2025-08-12 12:39:36 +02:00
Emil J fb024c4d55
Merge pull request #5135 from YosysHQ/emil/ast-ownership 
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
 2025-08-12 10:58:12 +02:00
KrystalDelusion 407d425114
Merge pull request #5024 from YosysHQ/krys/update_evals 
Updating test_cell
 2025-08-12 14:27:03 +12:00
Krystine Sherwin 1e6e25c81f
ci: Use correct build artifact 2025-08-12 12:43:14 +12:00
Krystine Sherwin c630f995d5
ci: Reduce test_cell count and use a seed 2025-08-12 11:17:00 +12:00
Krystine Sherwin ba01f7c64f
ci: Run test_cell 
Includes special cases for partially supported cells.
 2025-08-12 10:57:59 +12:00
Krystine Sherwin 1afe8d9f4d
celltypes: Comment pointing to ConstEval 
`CellTypes::eval()` is more generic but also more limited.  `ConstEval::eval()` requires more setup (both in code and at runtime) but has more complete support.
 2025-08-12 10:57:59 +12:00
Krystine Sherwin 20c2d2a6f3
test_cell: Add comment on $pmux 
`-simlib` also doesn't work.
 2025-08-12 10:57:59 +12:00
Martin Povišer c589714433
test_cell: Update to $macc_v2 2025-08-12 10:57:59 +12:00
Krystine Sherwin db4ffaffd2
consteval: Fix $bwmux handling 
If the cell type has a S signal and hasn't already been handled, use `CellTypes::eval(cell, A, B, S)`.
 2025-08-12 10:57:58 +12:00
Krystine Sherwin 014eadd8b9
test_cell: Fix $bweqx 2025-08-12 10:57:58 +12:00
Krystine Sherwin 22aa9fba3b
test_cell: Support more cell types 
Still unsupported:
- wide muxes (`$_MUX16_` and friends)

Partially supported types have comments in `test_cell.cc`.

Fix `CellTypes::eval() for `$_NMUX_`.
Fix `RTLIL::Cell::fixup_parameters()` for $concat, $bwmux and $bweqx.
 2025-08-12 10:57:58 +12:00
Krystine Sherwin 481ecb51a7
test_cell: Disable $macc testing 
Needs updating to `$macc_v2`.
 2025-08-12 10:57:58 +12:00
Jannis Harder 2d90e80b52
Merge pull request #5270 from zhanghongce/main 
Reorder the port wire declarations to follow the same order of the port declarations
 2025-08-11 15:35:25 +02:00
Emil J. Tywoniak 642e041f77 const2ast: fix for consistency with previous diagnostics behavior 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 99ab73424d verilog_location: rename location to Location to avoid conflict with Pass::location 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 5195f81257 ast: fix import node 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak df8422d244 verilog_lexer: refactor 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 740ed3fc1c ast: refactor 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 646c45e6b8 ast: remove null_check as dead code 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 25d2a8ce3a simplify: simplify 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 97bc0088d8 simplify: std::gcd 2025-08-11 13:34:10 +02:00
Krystine Sherwin d3e33a3be5 simplify.cc: Drop unused debug prints 
At least the ones added by this PR.  There are some unused debug prints that are *changed* by this PR, but I've left them.
 2025-08-11 13:34:10 +02:00
Krystine Sherwin 9b882c32c1 frontends/ast: More usage of auto 
For consistency.
 2025-08-11 13:34:10 +02:00
Krystine Sherwin 720f33271d docs: Update ubuntu apt-get 
Also mention CXXSTD fix for cygwin.
 2025-08-11 13:34:10 +02:00