Commit Graph

430 Commits

Author SHA1 Message Date
Akash Levy c55ee83992 Add Design.run_pass API 2025-05-08 07:20:02 -07:00
Akash Levy 5f5ed1b29e Merge upstream yosys 2025-04-21 17:36:24 -07:00
Akash Levy e241c9d513
Merge branch 'YosysHQ:main' into main 2025-04-10 14:28:10 -07:00
Krystine Sherwin ca57df8927
cutpoint: Add $scopeinfo cell
Also adds "blackbox" as a valid TYPE.
2025-04-11 04:12:34 +12:00
Krystine Sherwin 1ef9908a85
rtlil.cc: Fix box checks in selected_modules 2025-04-08 11:59:36 +12:00
Krystine Sherwin cd3b914132
Reinstate #4768
Revert the reversion so that we can fix the bugs that the PR missed.
2025-04-08 11:58:05 +12:00
Akash Levy 06c614a010
Merge branch 'YosysHQ:main' into main 2025-04-07 07:28:06 -07:00
Miodrag Milanović d49364d96f
Revert "Refactor full_selection" 2025-04-07 12:11:55 +02:00
Akash Levy 0dab4308a3 Actual merge here 2025-04-06 18:53:43 -07:00
Krystine Sherwin d8a9ad6860
Add Selection::clear() method
Use method in `select.cc` to reduce code duplication.
2025-04-05 10:56:01 +13:00
Akash Levy f218b5ba58 Revert "Represent memory size with size_t"
This reverts commit bb5f8415af.
2025-04-04 03:20:07 -07:00
Akash Levy bb5f8415af Represent memory size with size_t 2025-04-04 02:04:34 -07:00
Krystine Sherwin 68adac691d
rtlil.cc: Add comment to log_assert
Because the use of `RTLIL::AttrObject::get_blackbox_attribute()` is deprecated, but the assert is needed in case users are doing weird things.
2025-03-14 14:40:06 +13:00
Krystine Sherwin add5eba9b2
Design::selection_stack should never be empty
Add a `log_assert` for it in `Design::check()`.
Remove unneeded checks in other places.
2025-03-14 14:08:16 +13:00
Krystine Sherwin a30bacfcb1
Add Selection::complete_selection
Used to select all modules including boxes, set when both `full` and `boxes` are true in the constructor, pulling down `full_selection`.
Add `Selection::selects_all()` method as short hand for `full_selection || complete_selection`.
Update selection operations to account for complete selections.
Add static methods to `Selection` for creating a new empty/full/complete selection to make it clearer to users when doing so.
Use said static methods to replace most instances of the `Selection` constructor.
Update `Selection::optimize` to use
2025-03-14 14:08:15 +13:00
Krystine Sherwin d09ae42951
Fixing selections 2025-03-14 14:08:14 +13:00
Krystine Sherwin 091e9488fe
rtlil: Design::top_module() can be const
Since it doesn't change anything and is just a lookup.
2025-03-14 14:08:14 +13:00
Krystine Sherwin dac2bb7d4d
Use selection helpers
Catch more uses of selection constructor without assigning a design.
2025-03-14 14:08:13 +13:00
Krystine Sherwin a67b57bd64
rtlil: Add selection helpers
New methods on Design to push/pop selection instead of accessing the selection stack directly. Includes methods for pushing a full/complete/empty selection.
Also helper methods on modules to check `is_selected` and `is_selected_whole`.
2025-03-14 14:05:40 +13:00
Krystine Sherwin 3b1b09baf6
Can clean boxed modules
If a selection contains a boxed module, but does not select boxes, it should be removed from the selection.
2025-03-14 14:05:40 +13:00
Krystine Sherwin 2f907e8be4
Unify Design::selected_modules variants
Now uses two enums, one to control whether or not to include partially selected
modules (and what to do if they are encountered), and one to control whether or
not to include boxed modules (and what to do if they are encountered).

Mark Design::selected{modules, whole_modules}() deprecated and make them
provide warnings on boxes. There are a lot of places that use them and I can't
always tell which ones support boxed modules and which don't.
2025-03-14 14:05:40 +13:00
Krystine Sherwin 398afd102e
Refactor full_selection
The `Design::selected_*()` methods no longer unconditionally skip boxed modules.  Instead, selections are now box and design aware.
The selection constructor now optionally takes a design pointer, and has a new `selects_boxes` flag.  If the selection has an assigned design, then `Selection::selected_*()` will only return true for boxed modules if the selects_boxes flag is set.  A warning is raised if a selection is checked and no design is set.  Selections can change design via the `Selection::optimize()` method.
Most places that iterate over `Design::modules()` and check `Selection::selected_module()` should instead use `Design::selected_modules()`.
Since boxed modules should only ever be selected explicitly, and `full_selection` (now) refers to all non-boxed modules, `Selection::optimize()` will clear the `full_selection` flag if the `selects_boxes` flag is enabled, and instead explicitly selects all modules (including boxed modules).  This also means that `full_selection` will only get automatically applied to a design without any boxed modules.

These changes necessitated a number of changes to `select.cc` in order to support this functionality when operating on selections, in particular when combining selections (e.g. by union or difference).
To minimize redundancy, a number of places that previously iterated over `design->modules()` now push the current selection to the design, use `design->selected_modules()`, and then pop the selection when done.

Introduce `RTLIL::NamedObject`, to allow for iterating over all members of a module with a single iterator instead of needing to iterate over wires, cells, memories, and processes separately.
Also implement `Module::selected_{memories, processes, members}()` to match wires and cells methods.  The `selected_members()` method combines each of the other `selected_*()` methods into a single list.
2025-03-14 14:05:39 +13:00
Akash Levy e4066b784d Merge remote-tracking branch 'upstream/main' 2025-03-12 19:21:32 -07:00
Akash Levy 1e9adbe4b0 Add warning statements around the getParam issue 2025-03-12 19:16:10 -07:00
Akash Levy e1fc67a693 Improve the naming in instance add functions 2025-03-05 06:37:36 -08:00
Akash Levy 8117ab228e Use set for strpool_attribute to maintain ordering, but keep some backwards compatibility 2025-03-05 03:28:19 -08:00
Akash Levy 3a67468860 Use ordered set for src attrs when flattening 2025-03-04 23:47:48 -08:00
Akash Levy 7d33fd463b Add is_mostly_const to SigSpec 2025-02-13 11:11:33 -08:00
Martin Povišer 1d57a7cf6b macc_v2: Relax and fix cell check 2025-01-27 15:52:49 +01:00
Martin Povišer aabb4ea1df macc_v2: Fix checks and parameter padding 2025-01-27 13:08:19 +01:00
Martin Povišer cb8f855f34 rtlil: Fix macc_v2 cell check 2025-01-24 12:38:03 +01:00
Martin Povišer 61450e8b6e Update codebase for macc_v2 2025-01-24 12:38:03 +01:00
Martin Povišer 5882055899 macc_v2: Add C port 2025-01-24 12:38:03 +01:00
Martin Povišer c5fd96ebb0 macc_v2: Start new cell 2025-01-24 12:38:03 +01:00
Martin Povišer 08394c51a2 rtlil: Add const append helper 2025-01-24 12:38:03 +01:00
Akash Levy 4f41e01edc const modifier for pool of SigBit -> SigSpec conversion causing linkage errors on Mac 2024-12-20 11:56:10 -08:00
Akash Levy 2508d45f0b Use std::hash for RTLIL hashing 2024-12-19 21:54:57 -08:00
Akash Levy 1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J. Tywoniak 4e29ec1854 hashlib: acc -> eat 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
Akash Levy 4356eae4c9 Yosys sync 2024-12-04 14:16:55 -08:00
Krystine Sherwin 9925b27432
Goodbye guidelines (except GettingStarted)
Drop the parts that are being dropped.
Move the things that are being moved.
Also move the verilog stuff out of README and into the docs.
GettingStarted is less cut and dry, so hold off on that one.
2024-12-05 09:21:12 +13:00
Krystine Sherwin 1de5d98ae2
Reduce comparisons of size_t and int
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
2024-11-29 12:53:29 +13:00
Akash Levy 1a69c51c88
Merge branch 'YosysHQ:main' into main 2024-11-18 16:10:30 -08:00
Martin Povišer e82e5f8b13 rtlil: Adjust internal check for `$mem_v2` cells
There's a mismatch between what `kernel/mem.cc` emits for memories
with no read ports and what the internal RTLIL check expects.

The point of dispute it whether some of the parameters relating to read
ports have a zero-width value in this case. The `mem.cc` code says no,
the internal checker says yes.

Surveying the other `$mem_v2` parameters, and internal cell parameters
in general, I am inclined to side with the `mem.cc` code.

This breaks RTLIL compatibility but for an obscure edge case.
2024-11-08 15:18:43 +01:00
Alain Dargelas 43186b2c7a Returning unsigned int 2024-11-06 16:39:58 -08:00
Alain Dargelas 3ad51e06bc Using Yosys hash 2024-11-06 16:32:18 -08:00
Alain Dargelas 39c2d7aa60 RTLIL Module dump and hash 2024-11-06 15:48:24 -08:00
Akash Levy 7864c6dd34 vector fix for pyosys 2024-10-24 23:12:54 -07:00
Akash Levy 469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00