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16464 Commits

Author SHA1 Message Date
Lofty ca9793c85d analogdevices: double LUT RAM cost 2026-01-08 00:12:34 +00:00
Lofty 0f27d56f85 analogdevices: ignore $assert cells 2026-01-08 00:12:34 +00:00
Krystine Sherwin 1a29552fa4 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-01-08 00:12:34 +00:00
Krystine Sherwin 100e62ff56 analogdevices: Fixing up bram 
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
 2026-01-08 00:12:34 +00:00
Krystine Sherwin 25d7d0289e analogdevices: Add BRAM options 
Enable `-force-params`, and tidy up lutram mapping too.
 2026-01-08 00:12:34 +00:00
Krystine Sherwin 1d333796c1 memory_libmap: Add -force-params 
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
 2026-01-08 00:12:34 +00:00
Lofty 72a1d4ea3d analogdevices: LUT RAM only on positive edge 2026-01-08 00:12:34 +00:00
Lofty be7512279c analogdevices: DSP tweaks 2026-01-08 00:12:34 +00:00
Lofty 1375df7a2f analogdevices: DSP inference 2026-01-08 00:12:34 +00:00
Lofty 77fb166a36 analogdevices: remove cells_xtra 2026-01-08 00:12:34 +00:00
Lofty 722009638f analogdevices: timings for t40lp 2026-01-08 00:12:34 +00:00
Lofty 4f2b804185 analogdevices: use single tech param 2026-01-08 00:12:34 +00:00
Lofty fc494144ab analogdevices: expreso does not care about clock buffers 2026-01-08 00:12:34 +00:00
Lofty 25f6bdccf6 analogdevices: prepare for t40lp timings 2026-01-08 00:12:34 +00:00
Krystine Sherwin a957002498 analogdevices: Adding RBRAM2 and -tech 2026-01-08 00:12:34 +00:00
Krystine Sherwin a590811d50 analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2026-01-08 00:12:34 +00:00
Krystine Sherwin e44f555d3f analogdevices: Update lutram.ys test 2026-01-08 00:12:34 +00:00
Krystine Sherwin 7d198cbf60 analogdevices: Native LUTRAM primitives 2026-01-08 00:12:34 +00:00
Lofty 19d105904d analogdevices: LUTRAM config 2026-01-08 00:12:34 +00:00
Lofty 45d89c792f analogdevices: update timing model 2026-01-08 00:12:34 +00:00
Lofty 7bdb26feeb I thought I removed this... 2026-01-08 00:12:34 +00:00
Lofty e2478ed7da analogdevices: user retargeting 2026-01-08 00:12:34 +00:00
Lofty aac3c6dcc8 analogdevices: more housekeeping 2026-01-08 00:12:34 +00:00
Lofty 5ee5c4dc06 analogdevices: remove some extra cells! 2026-01-08 00:12:34 +00:00
Lofty 74da9a475e test suite 2026-01-08 00:12:34 +00:00
Lofty 970a4ee9e1 synth_analogdevices: remove scopeinfo cells 2026-01-08 00:12:34 +00:00
Lofty 0465c6c6aa Create synth_analogdevices 2026-01-08 00:12:34 +00:00
github-actions[bot] 35321cd292 Bump version 2026-01-07 00:25:36 +00:00
Emil J 0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00
Emil J 5c630a366d
Merge pull request #5555 from rocallahan/defer-redirects 
Defer redirecting cell outputs when merging cells in `opt_merge` untill after we've done a full pass over the cells.
 2026-01-06 18:48:16 +01:00
Robert O'Callahan 042ec1cf60 Defer redirecting cell outputs when merging cells in `opt_merge` until after we've done a full pass over the cells. 
This avoids changing `assign_map` and `initvals`, which are inputs to the hash function for `known_cells`,
while `known_cells` exists. Changing the hash function for a hashtable while it exists leads to
confusing behavior. That also means the exact behavior of `opt_merge` cannot be reproduced by a
parallel implementation.
 2026-01-06 16:21:48 +00:00
Emil J 2e1a2cfacb
Merge pull request #5561 from YosysHQ/emil/opt_expr-test-avoid-multiple-drivers 
opt_expr: avoid multiple drivers in test
 2026-01-06 14:54:55 +01:00
github-actions[bot] 1567526954 Bump version 2026-01-06 00:26:49 +00:00
Miodrag Milanović 1ccbd21ed8
Merge pull request #5587 from YosysHQ/update_abc 
Update ABC as per 2026-01-05
 2026-01-05 18:00:36 +01:00
Miodrag Milanovic 6e5a516051 Update ABC as per 2026-01-05 2026-01-05 16:34:45 +01:00
Miodrag Milanović eae00c19a8
Merge pull request #5579 from yrabbit/gw5-bsram-be-w 
Gowin. Implement byte enable.
 2026-01-05 11:10:03 +01:00
YRabbit 8a78f2f7c5 Gowin. Fix style. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2026-01-05 20:07:31 +10:00
Miodrag Milanović ab4381fba4
Merge pull request #5576 from rocallahan/idstring-pod 
Give `IdString` a default move constructor and make it a POD type.
 2026-01-05 11:05:56 +01:00
YRabbit ea90f54783 Gowin. Implement byte enable. 
Enable write port with byte enables for BSRAM primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2026-01-03 17:42:49 +10:00
github-actions[bot] 8101c87fab Bump version 2025-12-31 00:27:01 +00:00
Robert O'Callahan a6d696ba2b Give `IdString` a default move constructor and make it a POD type. 
Now that we're not refcounting `IdString`, it can use the default move constructor.
This lets us make `IdString` a POD type so it can be passed in registers
in the standard C++ ABI.
 2025-12-30 22:35:14 +00:00
Miodrag Milanović 582969b236
Merge pull request #5575 from YosysHQ/update_abc 
Update ABC as per 2025-12-29
 2025-12-30 10:00:49 +01:00
Miodrag Milanovic 55af32024d Update ABC as per 2025-12-29 2025-12-30 09:23:45 +01:00
github-actions[bot] 96549e5514 Bump version 2025-12-30 00:26:17 +00:00
Miodrag Milanović d523c88c3c
Merge pull request #5573 from rocallahan/increase-timeout 
Increase test timeout to 10 seconds
 2025-12-29 12:38:34 +01:00
Robert O'Callahan 99d7ab9c42 Increase test timeout to 10 seconds 
On my machine, this test regularly times out when doing "make -j" (which defaults to 128).
The high degree of parallelism seems to slow down the spwaning of ABC processes.
 2025-12-29 04:35:05 +00:00
github-actions[bot] 17ca71e1ab Bump version 2025-12-24 00:26:02 +00:00
Miodrag Milanović aa9991d3ee
Merge pull request #5571 from YosysHQ/micko/warning 
remove unused variable
 2025-12-23 16:32:10 +01:00
Miodrag Milanovic 4bc4e4eb41 remove unused variable 2025-12-23 15:47:35 +01:00
Miodrag Milanović 09f9e0e8d1
Merge pull request #5568 from rocallahan/abc-spawn-errno 
Print `errno` to help diagnose failure to spawn ABC
 2025-12-23 08:09:14 +01:00