Commit Graph

427 Commits

Author SHA1 Message Date
Akash Levy 1c15b51cee Fix define ID issue, needs undef first 2025-09-09 05:51:13 -07:00
Akash Levy 1b3375d8df Merge upstream in 2025-09-09 05:50:48 -07:00
Akash Levy 364a1f40a7 Don't warn about unboxed modules in RTLIL selected_modules 2025-08-22 11:07:19 -07:00
Akash Levy 56caf7cd84 Bump Yosys to latest 2025-08-13 13:37:37 -07:00
Emil J. Tywoniak c8e0ac0c61 ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
Akash Levy cc733fd11b Merge from upstream 2025-07-30 22:50:14 -07:00
Emil J 41295175dc
Merge pull request #5248 from calewis/try_unordereded_map
Use unordered_map instead of dict for IdString's char* to index storage.
2025-07-29 18:40:07 +02:00
Drew Lewis 2c8b4d7ad1 Use unordered_map instead of dict for IdString char* to index storage.
dict is pretty slow when you don't ever need to iterate the container in
order.  And the hashfunction for char* in dict hashes for every single
byte in the string, likely doing significantly more work than std::hash.
2025-07-29 10:48:44 +02:00
Robert O'Callahan f25f8fe7c4 In the Verilog backend, only sort modules that we're going to emit.
If you have a large design with a lot of modules and you use the Verilog
backend to emit modules one at a time to separate files, performance is
very low. The problem is that the Verilog backend calls `design->sort()`
every time, which sorts the contents of all modules, and this is slow
even when everything is already sorted.

We can easily fix this by only sorting the contents of modules that
we're actually going to emit.
2025-07-21 05:32:31 +00:00
Akash Levy d520cb42cc
Merge branch 'YosysHQ:main' into main 2025-05-22 10:30:58 -07:00
George Rennie 6331f92d00
Merge pull request #5101 from georgerennie/george/opt_expr_shift_ovfl
opt_expr: fix shift optimization with overflowing shift amount
2025-05-22 15:16:19 +01:00
George Rennie 98eec36921 kernel: add comments to as_int family of methods 2025-05-22 15:12:13 +01:00
Akash Levy 1f00bf0057 Bump yosys to latest 2025-05-15 14:44:26 -07:00
George Rennie 748600c167
small whitespace cleanup (#5119) 2025-05-14 15:18:57 +02:00
Akash Levy c55ee83992 Add Design.run_pass API 2025-05-08 07:20:02 -07:00
George Rennie 7cbe6ed048 kernel: add safer variants of as_int 2025-05-07 14:39:17 +02:00
Akash Levy e241c9d513
Merge branch 'YosysHQ:main' into main 2025-04-10 14:28:10 -07:00
Krystine Sherwin f042c36898
rtlil.h: Extra comment on helper enums
i.e. making explicit the ones that aren't intended for direct use.
2025-04-08 11:59:42 +12:00
Krystine Sherwin 7d7ee5d9bf
rtlil.h: Fix selection ctor ordering 2025-04-08 11:59:32 +12:00
Krystine Sherwin cd3b914132
Reinstate #4768
Revert the reversion so that we can fix the bugs that the PR missed.
2025-04-08 11:58:05 +12:00
Akash Levy 06c614a010
Merge branch 'YosysHQ:main' into main 2025-04-07 07:28:06 -07:00
Miodrag Milanović d49364d96f
Revert "Refactor full_selection" 2025-04-07 12:11:55 +02:00
Akash Levy 0dab4308a3 Actual merge here 2025-04-06 18:53:43 -07:00
Krystine Sherwin d8a9ad6860
Add Selection::clear() method
Use method in `select.cc` to reduce code duplication.
2025-04-05 10:56:01 +13:00
Krystine Sherwin dab67f84da
rtlil.h: Document selections 2025-04-05 10:46:09 +13:00
Akash Levy f218b5ba58 Revert "Represent memory size with size_t"
This reverts commit bb5f8415af.
2025-04-04 03:20:07 -07:00
Akash Levy bb5f8415af Represent memory size with size_t 2025-04-04 02:04:34 -07:00
Krystine Sherwin a3968d43f0
Drop deprecation on Design::selected_modules()
Instead, change the default `Design::selected_modules()` to match the behaviour (i.e. `selected_unboxed_modules_warn()`) because it's a lot of files to touch and they don't really _need_ to be updated.
Also change `Design::selected_whole_modules()` users over to `Design::selected_unboxed_whole_modules()`, except `attrmap` because I'm not convinced it should be ignoring boxes.  So instead, leave the deprecation warning for that one use and come back to the pass another time.
2025-03-14 14:08:56 +13:00
Krystine Sherwin add5eba9b2
Design::selection_stack should never be empty
Add a `log_assert` for it in `Design::check()`.
Remove unneeded checks in other places.
2025-03-14 14:08:16 +13:00
Krystine Sherwin 824f7146aa
Selecting a blackbox sets selects_boxes 2025-03-14 14:08:15 +13:00
Krystine Sherwin a30bacfcb1
Add Selection::complete_selection
Used to select all modules including boxes, set when both `full` and `boxes` are true in the constructor, pulling down `full_selection`.
Add `Selection::selects_all()` method as short hand for `full_selection || complete_selection`.
Update selection operations to account for complete selections.
Add static methods to `Selection` for creating a new empty/full/complete selection to make it clearer to users when doing so.
Use said static methods to replace most instances of the `Selection` constructor.
Update `Selection::optimize` to use
2025-03-14 14:08:15 +13:00
Krystine Sherwin 091e9488fe
rtlil: Design::top_module() can be const
Since it doesn't change anything and is just a lookup.
2025-03-14 14:08:14 +13:00
Krystine Sherwin dac2bb7d4d
Use selection helpers
Catch more uses of selection constructor without assigning a design.
2025-03-14 14:08:13 +13:00
Krystine Sherwin a67b57bd64
rtlil: Add selection helpers
New methods on Design to push/pop selection instead of accessing the selection stack directly. Includes methods for pushing a full/complete/empty selection.
Also helper methods on modules to check `is_selected` and `is_selected_whole`.
2025-03-14 14:05:40 +13:00
Krystine Sherwin 2f907e8be4
Unify Design::selected_modules variants
Now uses two enums, one to control whether or not to include partially selected
modules (and what to do if they are encountered), and one to control whether or
not to include boxed modules (and what to do if they are encountered).

Mark Design::selected{modules, whole_modules}() deprecated and make them
provide warnings on boxes. There are a lot of places that use them and I can't
always tell which ones support boxed modules and which don't.
2025-03-14 14:05:40 +13:00
Krystine Sherwin 398afd102e
Refactor full_selection
The `Design::selected_*()` methods no longer unconditionally skip boxed modules.  Instead, selections are now box and design aware.
The selection constructor now optionally takes a design pointer, and has a new `selects_boxes` flag.  If the selection has an assigned design, then `Selection::selected_*()` will only return true for boxed modules if the selects_boxes flag is set.  A warning is raised if a selection is checked and no design is set.  Selections can change design via the `Selection::optimize()` method.
Most places that iterate over `Design::modules()` and check `Selection::selected_module()` should instead use `Design::selected_modules()`.
Since boxed modules should only ever be selected explicitly, and `full_selection` (now) refers to all non-boxed modules, `Selection::optimize()` will clear the `full_selection` flag if the `selects_boxes` flag is enabled, and instead explicitly selects all modules (including boxed modules).  This also means that `full_selection` will only get automatically applied to a design without any boxed modules.

These changes necessitated a number of changes to `select.cc` in order to support this functionality when operating on selections, in particular when combining selections (e.g. by union or difference).
To minimize redundancy, a number of places that previously iterated over `design->modules()` now push the current selection to the design, use `design->selected_modules()`, and then pop the selection when done.

Introduce `RTLIL::NamedObject`, to allow for iterating over all members of a module with a single iterator instead of needing to iterate over wires, cells, memories, and processes separately.
Also implement `Module::selected_{memories, processes, members}()` to match wires and cells methods.  The `selected_members()` method combines each of the other `selected_*()` methods into a single list.
2025-03-14 14:05:39 +13:00
Akash Levy e4066b784d Merge remote-tracking branch 'upstream/main' 2025-03-12 19:21:32 -07:00
Martin Povišer 6da543a61a
Merge pull request #4818 from povik/macc_v2
Add `$macc_v2`
2025-03-12 22:55:40 +01:00
Akash Levy 8117ab228e Use set for strpool_attribute to maintain ordering, but keep some backwards compatibility 2025-03-05 03:28:19 -08:00
Akash Levy 3a67468860 Use ordered set for src attrs when flattening 2025-03-04 23:47:48 -08:00
Akash Levy 9d3b7f7474
Merge branch 'YosysHQ:main' into main 2025-02-26 09:51:44 -08:00
Jannis Harder 7cd822b7f5 rtlil: Add {from,to}_hdl_index methods to Wire
In the past we had the occasional bug due to some place not handling all
4 combinations of upto/downto and zero/nonzero start_offset correctly.
2025-02-18 17:08:45 +01:00
Akash Levy 7d33fd463b Add is_mostly_const to SigSpec 2025-02-13 11:11:33 -08:00
Martin Povišer 08394c51a2 rtlil: Add const append helper 2025-01-24 12:38:03 +01:00
Akash Levy bd439fc524 Reapply "Merge upstream"
This reverts commit e73d51dbf0.
2025-01-23 13:40:32 -08:00
Akash Levy e73d51dbf0 Revert "Merge upstream"
This reverts commit c58a50f880, reversing
changes made to a1c3c98773.
2025-01-21 05:28:36 -08:00
Akash Levy c58a50f880 Merge upstream 2025-01-21 04:36:34 -08:00
Emil J. Tywoniak 901935fbce hashlib: merge hash_ops with hash_top_ops for plugin compat 2025-01-14 21:41:33 +01:00
Akash Levy 57bf3a6f51
Merge branch 'YosysHQ:main' into main 2025-01-14 08:38:59 -08:00
Emil J. Tywoniak 4dbef95792 mark all hash_top methods nodiscard 2025-01-14 12:48:59 +01:00