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16822 Commits

Author SHA1 Message Date
nella a41f55eba7 Enable CSA for ORFS eval. 2026-04-02 15:17:39 +02:00
nella 0909e462c3 Fix test cases. 2026-04-01 18:40:51 +02:00
nella e4cb560163 Further CSA cleanup. 2026-04-01 13:30:34 +02:00
nella 09b6b7d24f Clang-Format CSA tree. 2026-04-01 11:04:57 +02:00
nella 9374ac325d Consolidate Wallace from booth and CSA. 2026-04-01 11:03:41 +02:00
nella 293feb55fa Invert. 2026-04-01 09:07:42 +02:00
nella 5f2407f449 Clarify. 2026-04-01 08:55:20 +02:00
Emil J. Tywoniak d0e381506c csa_tree: move to techmap 2026-04-01 08:28:40 +02:00
Emil J. Tywoniak eb477b2d56 csa_tree: refactor 2026-04-01 08:28:40 +02:00
nella c3bc2d88da Replace utf arrow with ascii arrow. 2026-03-30 15:47:34 +02:00
nella 537d67737d Cleaned up CSA tests. 2026-03-27 16:14:07 +01:00
nella 39d9be2df9 rm misc comments. 2026-03-20 16:56:07 +01:00
nella a73059c203 Move csa after alumacc. 2026-03-20 16:47:21 +01:00
nella 8181373ea3 CSA add alumacc related tests. 2026-03-19 17:45:56 +01:00
nella 4b0b1d35b5 CSA add support for macc and alu cells. 2026-03-19 17:44:56 +01:00
nella 1c1d782bf8 Consolidate csa tests. 2026-03-18 12:36:31 +01:00
nella 4ce8e7d1df Tighten csa tests. 2026-03-16 16:23:42 +01:00
nella 18c7cb094e Add csa to synth. 2026-03-16 15:39:54 +01:00
nella 4b037bda7a Add more robsutness tests. 2026-03-13 13:22:24 +01:00
nella 1f097a937f Add chain tests and tighten synthesis assertions for csa. 2026-03-13 13:14:32 +01:00
nella a7fcfc18fa Add sub chain support for csa trees. 2026-03-13 12:54:58 +01:00
nella b6ea0bb4cc Edge case tests. 2026-03-13 12:33:26 +01:00
nella 8d0ecbcdc0 Add csa synth tests. 2026-03-13 12:23:26 +01:00
nella 4381609684 Add structural tests for csa_tree. 2026-03-13 12:09:50 +01:00
nella 728403d1eb better balancing. 2026-03-13 11:06:48 +01:00
nella a180a0003f impl csa tree. 2026-03-11 11:31:40 +01:00
Miodrag Milanović de99d67bbd
Merge pull request #5733 from YosysHQ/update_abc 
Update ABC as per 2026-03-09
 2026-03-09 12:42:13 +00:00
Miodrag Milanovic fea0d18c0a Update ABC as per 2026-03-09 2026-03-09 13:04:45 +01:00
Emil J 2f1cdc2df9
Merge pull request #5728 from povik/tcl-set-result 
Replace deprecated Tcl API to fix use-after-free
 2026-03-06 13:36:48 +00:00
Martin Povišer 167c6c4585 Replace deprecated Tcl API to fix use-after-free 
Under Tcl 9.0 the Tcl_SetResult utility is a macro:

	#define Tcl_SetResult(interp, result, freeProc) \
		do { \
		    const char *__result = result; \
		    Tcl_FreeProc *__freeProc = freeProc; \
		    Tcl_SetObjResult(interp, Tcl_NewStringObj(__result, -1)); \
		    if (__result != NULL && __freeProc != NULL && __freeProc != TCL_VOLATILE) { \
			if (__freeProc == TCL_DYNAMIC) { \
			    Tcl_Free((char *)__result); \
			} else { \
			    (*__freeProc)((char *)__result); \
			} \
		    } \
		} while(0)

Temporaries constructed as part of the 'result' expression will be
dropped before the 'result' pointer is used. What was safe when
Tcl_SetResult was a function isn't safe with the macro definition.
Transition away from deprecated SetResult to calling
SetObjResult/MewStringObj directly.
 2026-03-06 11:52:17 +01:00
Lofty 050483a6b2
Merge pull request #5698 from YosysHQ/lofty/analogdevices 
synth_analogdevices: synthesis for Analog Devices EFLX FPGAs [sc-273]
 2026-03-06 08:57:59 +00:00
Miodrag Milanovic 602f3fd1a5 Add missing EOL 2026-03-06 09:10:55 +01:00
Miodrag Milanovic 52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Miodrag Milanović 95d738edc0
Merge pull request #5726 from YosysHQ/emil/double-expose-yosys_celltypes 
celltypes: include newcelltypes to allow legacy code access to migrat…
 2026-03-05 11:36:36 +00:00
Emil J 629bf3dffd
Merge pull request #5630 from apullin/array-assignment 
ast: Add support for array-to-array assignment
 2026-03-05 11:10:12 +00:00
Emil J. Tywoniak 23eb38fe3f celltypes: include newcelltypes to allow legacy code access to migrated yosys_celltypes 2026-03-05 11:59:20 +01:00
Lofty da83c93673 analogdevices: fix SHIFTX name 2026-03-05 05:37:13 +00:00
Lofty f3efa51b3e analogdevices: fix SHREG name 2026-03-05 05:37:13 +00:00
Lofty e2e8245be9 analogdevices: fix MUXF78 name 2026-03-05 05:37:13 +00:00
Lofty c747466a7a analogdevices: update missed T40LP timings 2026-03-05 05:37:13 +00:00
Lofty 91740645a9 analogdevices: update T40LP timings 2026-03-05 05:37:13 +00:00
Lofty 709746b184 analogdevices: update T16FFC timings 2026-03-05 05:37:13 +00:00
Lofty cd60dd4912 synth_analogdevices: update timing model and tests 2026-03-05 05:37:13 +00:00
Lofty 241db706e1 analogdevices: double LUT RAM cost 2026-03-05 05:37:13 +00:00
Lofty 3592d42d3b analogdevices: ignore $assert cells 2026-03-05 05:37:13 +00:00
Krystine Sherwin 5d3ed5a418 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-03-05 05:37:13 +00:00
Krystine Sherwin f06018306d analogdevices: Fixing up bram 
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
 2026-03-05 05:37:13 +00:00
Krystine Sherwin 95ef0cd788 analogdevices: Add BRAM options 
Enable `-force-params`, and tidy up lutram mapping too.
 2026-03-05 05:37:13 +00:00
Lofty 8a09cc5463 analogdevices: LUT RAM only on positive edge 2026-03-05 05:37:13 +00:00
Lofty dea8c275ff analogdevices: DSP tweaks 2026-03-05 05:37:12 +00:00