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17554 Commits

Author SHA1 Message Date
Aki-nyan 9b07d09583
Merge fac71a215c into 30fe16c7f1 2026-07-23 21:47:42 -07:00
Lofty 30fe16c7f1
Merge pull request #6061 from YosysHQ/lofty/remove-flowmap 
flowmap: remove
 2026-07-22 13:57:19 +00:00
Miodrag Milanović bc14cd7d18
Merge pull request #6062 from YosysHQ/mmicko/tests_only 
Add dependencies to gtests
 2026-07-22 13:39:05 +00:00
Miodrag Milanovic 5574994453 Add dependencies to gtests 2026-07-22 15:03:12 +02:00
Lofty f0b5225134 flowmap: remove 2026-07-22 13:50:33 +01:00
Lofty f9023e92b4
Merge pull request #6059 from drewbabel/fix-xilinx-srl-fdre-enable 
xilinx_srl: keep the clock enable on FDRE shift registers
 2026-07-22 10:33:29 +00:00
Lofty b914a7802e
Merge pull request #5782 from YosysHQ/lofty/abc-refactor-1 
abc: remove -fast (again)
 2026-07-21 09:26:10 +00:00
Lofty 45e1de36b4 abc: remove -fast (again) 2026-07-21 09:50:14 +01:00
drewbabel 3006280d70
xilinx_srl: keep the clock enable on FDRE shift registers 
run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.

Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
 2026-07-20 23:59:40 -07:00
Miodrag Milanović e2c27aaafa
Merge pull request #6042 from YosysHQ/krys/symfpu 
Add `symfpu` pass
 2026-07-20 10:20:23 +00:00
Miodrag Milanovic cfd80cb48e Update constids to fix leaks 2026-07-20 11:53:55 +02:00
Miodrag Milanovic a7cfabd405 Fix gcc compile errors 2026-07-20 10:29:41 +02:00
Miodrag Milanović 3ce3196265
Merge pull request #6056 from YosysHQ/mmicko/ci_skip_update 
CI: back to using official action
 2026-07-20 07:08:47 +00:00
Miodrag Milanovic 60403f35ca CI: back to using official action 2026-07-20 08:23:37 +02:00
Emil J 5f29546d80
Merge pull request #6050 from YosysHQ/emil/autoname-rewrite 
autoname: rewrite
 2026-07-19 22:10:02 +00:00
Krystine Sherwin c2237447bf
symfpu: Drop libs/ from symfpu includes 2026-07-20 09:58:04 +12:00
myrtle a0fbe6e133
Merge pull request #6054 from YosysHQ/gatecat/nexus-radiant-fix 
nexus: Fix Radiant netlist compatibility
 2026-07-19 13:22:46 +00:00
gatecat 15c54ae15e nexus: Fix Radiant netlist compatibility 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-19 12:44:40 +02:00
Catherine 6f7123d1d2
Merge pull request #6053 from whitequark/fix-libffi-detection 
Fix DPI-C support broken in v0.67
 2026-07-18 14:19:32 +00:00
Catherine 21aa69f448 Fix DPI-C support broken in v0.67. 
Fixes #6052.
 2026-07-17 22:21:59 +00:00
Emil J. Tywoniak 8565451ef9 autoname: selection determines what gets renamed, not the name it gets renamed to 2026-07-17 22:48:46 +02:00
Emil J. Tywoniak fb0bb160ad autoname: rewrite 2026-07-17 12:02:43 +02:00
Lofty 45ea2b8d6c
Merge pull request #6047 from olby/mul2dsp-commute-first 
mul2dsp: normalize operand order before min-width checks
 2026-07-15 15:47:08 +00:00
Johan Olby 63457de80e
mul2dsp: normalize operand order 
Move the operand commute that puts the wider operand on A ahead of the
min-width checks. Checking the min-widths first made an asymmetric rule
(DSP_A_MINWIDTH != DSP_B_MINWIDTH) match only products that already had the
wider operand on A; a product in the other order was rejected before the
normalization.
 2026-07-15 16:21:07 +02:00
Miodrag Milanović 9914b6fa25
Merge pull request #6044 from YosysHQ/mmicko/codeql 
codeql: do not generate reports for 3rd party code
 2026-07-15 07:12:44 +00:00
Miodrag Milanovic 6fa6849734 codeql: do not generate reports for 3rd party code 2026-07-15 08:54:10 +02:00
Miodrag Milanović 0135a61db3
Merge pull request #6043 from YosysHQ/mmicko/sv-elab 
Update sv-elab to 3dddccd
 2026-07-15 06:43:02 +00:00
Miodrag Milanovic eb3a15cd8c Update sv-elab to 3dddccd 2026-07-15 08:24:46 +02:00
Krystine Sherwin 9dd5c3a6a4
symfpu: Run pre-commit 2026-07-15 14:56:11 +12:00
Krystine Sherwin 6730b3ec54
libs/symfpu: Fixup submodule 2026-07-15 14:52:53 +12:00
Krystine Sherwin c3043b1ce5
symfpu: whitespace 2026-07-15 14:50:33 +12:00
Krystine Sherwin e6bd07a49a
tests/symfpu: Switch to generate_mk.py 2026-07-15 14:50:33 +12:00
Krystine Sherwin 952d01b821
libs/symfpu: tinyAfterRounding 2026-07-15 14:50:32 +12:00
Krystine Sherwin d5b6a38f65
symfpu: Missed a space 2026-07-15 14:50:32 +12:00
Krystine Sherwin 7b5d334603
symfpu_convert: Handle signed ints 
Use input wire `is_signed` to select between signed and unsigned handling.
 2026-07-15 14:50:32 +12:00
Krystine Sherwin 50c4a057b2
symfpu: Use ubv for convert flags 2026-07-15 14:50:31 +12:00
Krystine Sherwin 675087937f
symfpu: Convert with flags 2026-07-15 14:50:31 +12:00
Krystine Sherwin dfec87e6a3
symfpu: Add symfpu_convert 
Convert one input to three outputs (int -> float, float -> int, float -> float).
No rounding mode, no flags (yet).
 2026-07-15 14:50:31 +12:00
Krystine Sherwin 613d95b909
symfpu: Test comparisons 2026-07-15 14:50:30 +12:00
Krystine Sherwin 7a6b36b670
symfpu: Add -compare mode 
Also `min` and `max` ops.  RISC-V uses IEEE 754-2019 semantics where `min(+0,-0) == -0` and `max(+0,-0) == +0` so we do the same here.  We could make it optional, but as I understand it the newer behavior is still backwards compatible (since previously it was valid to have selected either).
 2026-07-15 14:50:30 +12:00
Krystine Sherwin 16f6e8dc6a
Add symfpu -classify 
Add description text for standard `symfpu` signature.
 2026-07-15 14:50:30 +12:00
Krystine Sherwin 4134436a9f
tests/symfpu: Extra muladd tests 
Switch inputs back to `anyseq`, and add coverage for muladd with constant multiplier output and varying addend (also an assertion).
Use an `ifdef` to control clocked properties (because of the assertion, it's no longer just covers that are clocked).
 2026-07-15 14:50:29 +12:00
Krystine Sherwin b66c0dcc97
tests/symfpu: Testing sqrt 
Coverage supports `sqrt`, including new general rounding detection instead of just inf/ebmin/zero (since they aren't possible with `sqrt`).
More `sqrt` assertions, as well as the addition of `altsqrt` verification.
Some adjustments of macros.
 2026-07-15 14:50:29 +12:00
Krystine Sherwin 9943484dbc
symfpu: Add altsqrt 
No denormalization here.  That can be a problem for later (or not at all).
 2026-07-15 14:50:29 +12:00
Krystine Sherwin 91928a7329
symfpu: Add alt2div 
`altdiv` but without denormalization, because as it turns out HardFloat unpacks subnorms in the same way, so lets just support both styles.
 2026-07-15 14:50:29 +12:00
Krystine Sherwin db676a2eae
symfpu: Add altdiv 2026-07-15 14:50:28 +12:00
Krystine Sherwin 3f22dabb8d
tests/symfpu: Add cover checks 
Include mask/map for abc inputs (and switch to `anyconst` instead of `anyseq`).
Add false divide check for mantissa.
Covers aren't currently being tested by anything (and have to be removed for `sat`), but I've been using it locally with SBY to confirm that the different edge cases are able to be verified (e.g. when verifying HardFloat against symfpu while using the masked inputs to reduce solver time).
 2026-07-15 14:50:28 +12:00
Krystine Sherwin b818e1c8ca
Fix tininess when rounding to ebmin 2026-07-15 14:50:28 +12:00
Krystine Sherwin 5751023b6c
tests/symfpu: UF to ebmin is valid 2026-07-15 14:50:27 +12:00
Krystine Sherwin 70dad5a06e
Don't raise DZ when left is inf 2026-07-15 14:50:27 +12:00