run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.
Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
Move the operand commute that puts the wider operand on A ahead of the
min-width checks. Checking the min-widths first made an asymmetric rule
(DSP_A_MINWIDTH != DSP_B_MINWIDTH) match only products that already had the
wider operand on A; a product in the other order was rejected before the
normalization.
Map $macc_v2 cells (one signed <=27x18 product + one <=48-bit addend)
to MULTALU27X18 with the C addend enabled, so a*b+c maps to a single
DSP block instead of a multiply + fabric adder.
The C addend requires DYN_C_SEL("TRUE") + CSEL=1 (gowin_pack reads the
CSEL port, not the C_SEL parameter).
alumacc + macc techmap run before wreduce for gw5a, so $mul and $add
ports still have matching widths when alumacc tries to merge them.
Running after wreduce breaks the merge: wreduce narrows $mul Y (48->45)
but not $add A (stays 48), and alumacc can't merge mismatched widths.
- with PCF support in nextpnr fabulous, `-iopad` is now the default
- supply further mapping using `-extra-plib`
Signed-off-by: Leo Moser <leomoser99@gmail.com>
- this allows to map to any memories
- to map legacy register files, use: `-extra-plib regfile.v -extra-mlibmap ram_regfile.txt -extra-map regfile_map.v`
Signed-off-by: Leo Moser <leomoser99@gmail.com>
The concept of 'COMPLEX_DFF' is deprecated. Instead, simply specify the supported flip-flops using `-ff <cell_type_pattern> <init_values>` and supply the mapping file.
Signed-off-by: Leo Moser <leomoser99@gmail.com>