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529 Commits

Author SHA1 Message Date
Akash Levy 7847b1b2eb
Merge pull request #30 from alaindargelas/macro_power 
Simulation information for macro power
 2024-12-04 10:01:04 -08:00
Alain Dargelas 350b04daa3 Ignore unused modules 2024-12-03 13:00:14 -08:00
Akash Levy e0cef06b52
Merge branch 'YosysHQ:main' into main 2024-12-02 19:39:14 -05:00
Miodrag Milanovic 912b38eedb verific: Handle crash when using empty box option 2024-12-02 15:45:12 +01:00
Akash Levy ead4b34c3c Add stack include to decorate_loops.h 2024-12-01 16:50:51 -05:00
Akash Levy 620bf51c50
Merge pull request #29 from alaindargelas/loop_info_3 
Selective boolopt
 2024-12-01 12:36:09 -05:00
Akash Levy 6e88c689f2
Merge branch 'YosysHQ:main' into main 2024-12-01 12:32:07 -05:00
Alain Dargelas c32d0a412c Selective boolopt 2024-11-25 15:08:42 -08:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
Akash Levy c3d6821f7d Removing compiler warnings and errors 2024-11-22 20:04:39 -08:00
Alain Dargelas 97f5ef2056 indent 2024-11-21 11:31:36 -08:00
Alain Dargelas dc9d61ed61 Loop info 2024-11-21 11:24:00 -08:00
Alain Dargelas 179bd25235 Loop info 2024-11-21 11:23:13 -08:00
Alain Dargelas dde6a8d8f1 Loop info 2024-11-21 11:20:40 -08:00
Miodrag Milanovic d6bd521487 verific : VHDL assert DFF initial value set on Verific library patch side 2024-11-21 13:43:26 +01:00
Akash Levy bbbc292209 Smallfixes 2024-11-20 21:10:58 -08:00
Akash Levy 6a7e2d2572 Beginnings of UPF support 2024-11-20 20:36:29 -08:00
Akash Levy 2b39770f57 Update flags to be better 2024-11-20 20:36:12 -08:00
Akash Levy 6be73e5c2e Updates 2024-11-15 19:02:06 -08:00
Mike Inouye 06e3ac4415 Fix bug when setting Verific runtime string flags. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-11-12 18:46:26 +00:00
Akash Levy 83234d24f7 Switch from Synopsys register naming to preserve 2024-11-11 17:06:56 -08:00
Akash Levy 894c9816d3 Improve naming: big fix 2024-11-11 17:06:11 -08:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
Alain Dargelas 615f523ef4 pass no_split_complex_ports to hierarchy command 2024-10-29 13:37:03 -07:00
Akash Levy 5e606722e3 Get autoidx reset working 2024-10-28 16:30:47 -07:00
Akash Levy 038c562493 VHDL support fix 2024-10-25 11:32:52 -07:00
Akash Levy 8e667e2e9f Add documentation for VHDL library directory 2024-10-23 23:53:21 -07:00
Akash Levy 17c8567b02 Really tiny fixes 2024-10-23 22:03:00 -07:00
Akash Levy 3d127dff4a Add set VHDL default library path 2024-10-21 01:22:56 -07:00
Akash Levy c94eac14b9 Remove GHDL and add mixed SV-VHDL support 2024-10-20 23:29:33 -07:00
Akash Levy e2659247fc Verific UPF eval working 2024-10-17 04:40:38 -07:00
Akash Levy 469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00
Emil J caf56ca3e8
Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip 
Represent string constants as strings
 2024-10-14 06:42:54 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Miodrag Milanovic 8d2b63bb8a Set VHDL assert condition initial state if fed by FF 2024-10-11 16:32:21 +02:00
Akash Levy 48cb802599 Undo bound removal 2024-10-10 13:34:18 -07:00
Akash Levy dd487ca8a1 Updating Yosys 2024-10-03 01:46:09 -07:00
Akash Levy 5038bfa2af Fix minor whitespace thing 2024-10-03 00:29:16 -07:00
Akash Levy ec296736f5 Simplify multiport 2024-10-02 22:19:09 -07:00
Akash Levy 400ae0bbab Prune RAM dimensions 2024-10-02 03:44:57 -07:00
Akash Levy 8bf86e8d1f Undo 2024-10-02 03:30:30 -07:00
Akash Levy ff0fd570d8 Revert mem but fix Verific frontend to remove ugliness 2024-10-02 01:17:01 -07:00
Akash Levy 0610d6ccc2 Smallfix to get GHDL working 2024-09-27 06:38:42 -07:00
Akash Levy bb2cdd61fe Fix GHDL and bump yosys-slang 2024-09-27 04:43:59 -07:00
Akash Levy 5a27db1463 Smallfix 2024-09-27 03:31:30 -07:00
Akash Levy f6d577aed1 Fix GHDL support 2024-09-27 03:14:15 -07:00
Akash Levy 0fd6e29e8e Fixups 2024-09-23 04:25:10 -07:00
Akash Levy 0b8d951493 Add synopsys VHDL libs by default in GHDL 2024-09-23 04:05:27 -07:00
Akash Levy 69bf7875dd Small edits 2024-09-22 07:52:58 -07:00
Akash Levy d655766c49 Smallfix 2024-09-22 06:57:28 -07:00