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17567 Commits

Author SHA1 Message Date
Iztok Jeras 6f1f3752e4 dfflibmap: added warning about clear/preset priority mismatch 2026-07-22 22:22:28 +02:00
Iztok Jeras 64ef4babf3 dfflibmap: extended tests with same testcases as dlatchmap 2026-07-22 22:22:28 +02:00
Iztok Jeras 92d4f60977 dlatchlibmap: added more formal testscases 2026-07-22 22:22:28 +02:00
Iztok Jeras 6b44f4321e dfflibmap: picking first instead of last cell with smallest area 
In a standard cell library cells are usually ordered from weakest to strongest.
Sometimes the two weakest cells have the same area.
Previously the stroner (last) of the two was selected,
now the weaker (first is selected).
 2026-07-22 22:22:28 +02:00
Iztok Jeras 2e7ead5453 dfflibmap: collected copies of the same code into a function 2026-07-22 22:22:28 +02:00
Iztok Jeras a707d57576 dfflibmap: updated dlatchlibmap tests so they pass 2026-07-22 22:22:28 +02:00
Iztok Jeras fc29a9b402 dlatchlibmap: modified copies of dfflibmap* test files for dlatchlibmap tests 2026-07-22 22:22:28 +02:00
Iztok Jeras 3fdbbf70ea dlatchlibmap: making a copy of test files dfflibmap* to dlatchlibmap* 2026-07-22 22:22:28 +02:00
Iztok Jeras e78f85f33a dlatchlibmap: fixing failing test 'liberty/dff.lib' by updating the golden log output 2026-07-22 22:22:28 +02:00
Iztok Jeras 4a6ae2fdd4 frontends/liberty: support all \$_LATCH* type cells (copy/modify from FF code) 2026-07-22 22:22:28 +02:00
Iztok Jeras 4f9b346151 dfflibmap: simpler handling of cells with inverted data input polarity 2026-07-22 22:22:28 +02:00
Iztok Jeras 65f9d017ec dfflibmap: recommend running opt_merge pass after dfflibmap 2026-07-22 22:22:28 +02:00
Iztok Jeras 76ec42122b dfflibmap: support for mapping latch cells 2026-07-22 22:22:28 +02:00
Iztok Jeras 23ead8ef4c dfflibmap: fixing apparent typo in testcase 2026-07-22 22:22:28 +02:00
Iztok Jeras 0a5e35257e dfflegalize: make it explicit in the documentation, that the pass operates on FFs and LATCHes 2026-07-22 22:22:28 +02:00
Iztok Jeras a071afd938 documentation: avoid documentation rendering issue 2026-07-22 22:22:28 +02:00
Lofty 30fe16c7f1
Merge pull request #6061 from YosysHQ/lofty/remove-flowmap 
flowmap: remove
 2026-07-22 13:57:19 +00:00
Miodrag Milanović bc14cd7d18
Merge pull request #6062 from YosysHQ/mmicko/tests_only 
Add dependencies to gtests
 2026-07-22 13:39:05 +00:00
Miodrag Milanovic 5574994453 Add dependencies to gtests 2026-07-22 15:03:12 +02:00
Lofty f0b5225134 flowmap: remove 2026-07-22 13:50:33 +01:00
Lofty f9023e92b4
Merge pull request #6059 from drewbabel/fix-xilinx-srl-fdre-enable 
xilinx_srl: keep the clock enable on FDRE shift registers
 2026-07-22 10:33:29 +00:00
Lofty b914a7802e
Merge pull request #5782 from YosysHQ/lofty/abc-refactor-1 
abc: remove -fast (again)
 2026-07-21 09:26:10 +00:00
Lofty 45e1de36b4 abc: remove -fast (again) 2026-07-21 09:50:14 +01:00
drewbabel 3006280d70
xilinx_srl: keep the clock enable on FDRE shift registers 
run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.

Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
 2026-07-20 23:59:40 -07:00
Miodrag Milanović e2c27aaafa
Merge pull request #6042 from YosysHQ/krys/symfpu 
Add `symfpu` pass
 2026-07-20 10:20:23 +00:00
Miodrag Milanovic cfd80cb48e Update constids to fix leaks 2026-07-20 11:53:55 +02:00
Miodrag Milanovic a7cfabd405 Fix gcc compile errors 2026-07-20 10:29:41 +02:00
Miodrag Milanović 3ce3196265
Merge pull request #6056 from YosysHQ/mmicko/ci_skip_update 
CI: back to using official action
 2026-07-20 07:08:47 +00:00
Miodrag Milanovic 60403f35ca CI: back to using official action 2026-07-20 08:23:37 +02:00
Emil J 5f29546d80
Merge pull request #6050 from YosysHQ/emil/autoname-rewrite 
autoname: rewrite
 2026-07-19 22:10:02 +00:00
Krystine Sherwin c2237447bf
symfpu: Drop libs/ from symfpu includes 2026-07-20 09:58:04 +12:00
myrtle a0fbe6e133
Merge pull request #6054 from YosysHQ/gatecat/nexus-radiant-fix 
nexus: Fix Radiant netlist compatibility
 2026-07-19 13:22:46 +00:00
gatecat 15c54ae15e nexus: Fix Radiant netlist compatibility 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-19 12:44:40 +02:00
Catherine 6f7123d1d2
Merge pull request #6053 from whitequark/fix-libffi-detection 
Fix DPI-C support broken in v0.67
 2026-07-18 14:19:32 +00:00
Catherine 21aa69f448 Fix DPI-C support broken in v0.67. 
Fixes #6052.
 2026-07-17 22:21:59 +00:00
Emil J. Tywoniak 8565451ef9 autoname: selection determines what gets renamed, not the name it gets renamed to 2026-07-17 22:48:46 +02:00
Emil J. Tywoniak fb0bb160ad autoname: rewrite 2026-07-17 12:02:43 +02:00
Lofty 45ea2b8d6c
Merge pull request #6047 from olby/mul2dsp-commute-first 
mul2dsp: normalize operand order before min-width checks
 2026-07-15 15:47:08 +00:00
Johan Olby 63457de80e
mul2dsp: normalize operand order 
Move the operand commute that puts the wider operand on A ahead of the
min-width checks. Checking the min-widths first made an asymmetric rule
(DSP_A_MINWIDTH != DSP_B_MINWIDTH) match only products that already had the
wider operand on A; a product in the other order was rejected before the
normalization.
 2026-07-15 16:21:07 +02:00
Miodrag Milanović 9914b6fa25
Merge pull request #6044 from YosysHQ/mmicko/codeql 
codeql: do not generate reports for 3rd party code
 2026-07-15 07:12:44 +00:00
Miodrag Milanovic 6fa6849734 codeql: do not generate reports for 3rd party code 2026-07-15 08:54:10 +02:00
Miodrag Milanović 0135a61db3
Merge pull request #6043 from YosysHQ/mmicko/sv-elab 
Update sv-elab to 3dddccd
 2026-07-15 06:43:02 +00:00
Miodrag Milanovic eb3a15cd8c Update sv-elab to 3dddccd 2026-07-15 08:24:46 +02:00
Krystine Sherwin 9dd5c3a6a4
symfpu: Run pre-commit 2026-07-15 14:56:11 +12:00
Krystine Sherwin 6730b3ec54
libs/symfpu: Fixup submodule 2026-07-15 14:52:53 +12:00
Krystine Sherwin c3043b1ce5
symfpu: whitespace 2026-07-15 14:50:33 +12:00
Krystine Sherwin e6bd07a49a
tests/symfpu: Switch to generate_mk.py 2026-07-15 14:50:33 +12:00
Krystine Sherwin 952d01b821
libs/symfpu: tinyAfterRounding 2026-07-15 14:50:32 +12:00
Krystine Sherwin d5b6a38f65
symfpu: Missed a space 2026-07-15 14:50:32 +12:00
Krystine Sherwin 7b5d334603
symfpu_convert: Handle signed ints 
Use input wire `is_signed` to select between signed and unsigned handling.
 2026-07-15 14:50:32 +12:00