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16510 Commits

Author SHA1 Message Date
Emil J 317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J 5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
Miodrag Milanović 2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy 
Avoid spurious copy in `IdStringCollector::trace_named()`
 2026-01-21 08:30:07 +01:00
Robert O'Callahan 2c0448a81b Avoid spurious copy in `IdStringCollector::trace_named()` 2026-01-21 03:31:56 +00:00
github-actions[bot] 57ac113b7f Bump version 2026-01-21 00:27:51 +00:00
Miodrag Milanović bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017 
verific: add explicit System Verilog 2017 option
 2026-01-20 14:44:46 +01:00
Miodrag Milanovic d0fa4781c6 verific: Fix -sv2017 message and formatting 2026-01-20 08:07:26 +01:00
github-actions[bot] 49e5950791 Bump version 2026-01-20 00:26:10 +00:00
Miodrag Milanovic cc3038f468 verific: Fix -sv2017 message 2026-01-19 16:32:46 +01:00
Miodrag Milanović 2bde91b6ef
Merge pull request #5618 from YosysHQ/update_abc 
Update ABC as per 2026-01-19
 2026-01-19 15:45:02 +01:00
nella 67d10a41e8
Merge pull request #5617 from YosysHQ/emil/consteval-description 
consteval: describe
 2026-01-19 14:56:24 +01:00
Miodrag Milanovic 691983be14 Update ABC as per 2026-01-19 2026-01-19 12:08:24 +01:00
Emil J 7880f31acb
Merge pull request #5531 from YosysHQ/emil/shuffle-contributing-docs 
docs: shuffle and expand contributing info
 2026-01-19 12:02:49 +01:00
Emil J. Tywoniak c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Emil J. Tywoniak befadf6d4d consteval: describe 2026-01-19 12:00:18 +01:00
Miodrag Milanović 9355fa5037
Merge pull request #5616 from rocallahan/fix-unused-var-warning 
Fix warning about unused variable in `dffunmap`.
 2026-01-19 08:24:48 +01:00
Robert O'Callahan 28c199fbbd Fix warning about unused variable in `dffunmap`. 2026-01-19 03:25:09 +00:00
KrystalDelusion 8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err 
Improve error handling in sim
 2026-01-19 09:51:12 +13:00
Miodrag Milanovic d095d2c405 verific: add explicit System Verilog 2017 option 2026-01-16 07:56:53 +01:00
Natalia ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Natalia d5e1647d11 fix tests with truncation issues 2026-01-14 18:03:30 -08:00
github-actions[bot] 967b47d984 Bump version 2026-01-15 00:24:54 +00:00
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width 
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
 2026-01-14 14:58:53 -08:00
Natalia 60ac3670cb Fix truncation issue in opt_balance_tree pass 
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.

For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)

Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
 2026-01-14 13:14:56 -08:00
nella 763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string 
Add rtlil string getters
 2026-01-14 19:00:47 +01:00
nella 210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00
github-actions[bot] 4c1a18f01d Bump version 2026-01-14 06:40:44 +00:00
Natalia Kokoromyti 6aef8ea8ab Add missing <deque> include for MSVC compatibility 2026-01-13 15:31:46 -08:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Emil J 71feb2a2a1
Merge pull request #5604 from YosysHQ/emil/read_verilog-remove-log 
read_verilog: remove log I left behind by accident
 2026-01-13 17:48:30 +00:00
Emil J. Tywoniak 83c1364eeb read_verilog: remove log I left behind by accident 2026-01-13 18:47:23 +01:00
Emil J 8da113b7f0
Merge pull request #5502 from YosysHQ/emil/digit-separator 
Use digit separators for large decimal integers
 2026-01-13 17:42:24 +00:00
Emil J d9956b20f8
Merge pull request #5603 from YosysHQ/emil/makefile-no-ast-header 
Makefile: no longer install ast.h and ast_binding.h
 2026-01-13 17:18:40 +00:00
Emil J ff3c24fcdc
Merge pull request #5521 from YosysHQ/emil/merge-queues 
.github: trigger everything that triggers on main or PRs on merge queue
 2026-01-13 17:22:37 +01:00
Emil J 5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire 
Add autowires in genblk/for expension
 2026-01-13 16:40:22 +01:00
Emil J. Tywoniak 8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Emil J. Tywoniak 21e6833010 Makefile: no longer install ast.h and ast_binding.h 2026-01-13 16:33:11 +01:00
Miodrag Milanović 8f00c1824f
Merge pull request #5602 from YosysHQ/year_update 
Update year in banner and license
 2026-01-13 15:30:42 +01:00
Miodrag Milanovic 0e6973037d Update year in banner and license 2026-01-13 14:23:51 +01:00
nella b332279baf
Merge pull request #5592 from YosysHQ/gus/5503-yw-load-error-msg 
More helpful error messages when loading Yosys Witness files with `yosys-smtbmc`
 2026-01-13 12:00:06 +01:00
Miodrag Milanović 77005b69a2
Merge pull request #5601 from YosysHQ/release/v0.61 
Release version 0.61
 2026-01-13 09:39:50 +01:00
Miodrag Milanovic b08e044994 Next dev cycle 2026-01-13 09:24:49 +01:00
Miodrag Milanovic 5ae48ee25f Release version 0.61 2026-01-13 08:35:02 +01:00
Miodrag Milanović 51b210c93c
Merge pull request #5600 from YosysHQ/fix_musllinux 
musllinux fix so wheels build can work
 2026-01-13 07:08:04 +01:00
github-actions[bot] 78cbc21b94 Bump version 2026-01-13 00:22:49 +00:00
Emil J. Tywoniak b8497217bc contributing: review process 2026-01-13 00:16:58 +01:00
Emil J cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux 
add lut2bmux
 2026-01-12 16:09:13 +01:00
Miodrag Milanovic b3b71df07c musllinux fix so wheels build can work 2026-01-12 15:38:45 +01:00
Miodrag Milanović 72690062a1
Merge pull request #5599 from YosysHQ/musllinux_fix 
musllinux fix so wheels build can work
 2026-01-12 14:00:00 +01:00
Emil J f193dd0a28
Merge pull request #5594 from rocallahan/sdc-workaround 
Check for missing port in SDC code to work around compiler bug
 2026-01-12 11:22:25 +01:00