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16794 Commits

Author SHA1 Message Date
Emil J 2f1cdc2df9
Merge pull request #5728 from povik/tcl-set-result 
Replace deprecated Tcl API to fix use-after-free
 2026-03-06 13:36:48 +00:00
Martin Povišer 167c6c4585 Replace deprecated Tcl API to fix use-after-free 
Under Tcl 9.0 the Tcl_SetResult utility is a macro:

	#define Tcl_SetResult(interp, result, freeProc) \
		do { \
		    const char *__result = result; \
		    Tcl_FreeProc *__freeProc = freeProc; \
		    Tcl_SetObjResult(interp, Tcl_NewStringObj(__result, -1)); \
		    if (__result != NULL && __freeProc != NULL && __freeProc != TCL_VOLATILE) { \
			if (__freeProc == TCL_DYNAMIC) { \
			    Tcl_Free((char *)__result); \
			} else { \
			    (*__freeProc)((char *)__result); \
			} \
		    } \
		} while(0)

Temporaries constructed as part of the 'result' expression will be
dropped before the 'result' pointer is used. What was safe when
Tcl_SetResult was a function isn't safe with the macro definition.
Transition away from deprecated SetResult to calling
SetObjResult/MewStringObj directly.
 2026-03-06 11:52:17 +01:00
Lofty 050483a6b2
Merge pull request #5698 from YosysHQ/lofty/analogdevices 
synth_analogdevices: synthesis for Analog Devices EFLX FPGAs [sc-273]
 2026-03-06 08:57:59 +00:00
Miodrag Milanovic 602f3fd1a5 Add missing EOL 2026-03-06 09:10:55 +01:00
Miodrag Milanovic 52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Miodrag Milanović 95d738edc0
Merge pull request #5726 from YosysHQ/emil/double-expose-yosys_celltypes 
celltypes: include newcelltypes to allow legacy code access to migrat…
 2026-03-05 11:36:36 +00:00
Emil J 629bf3dffd
Merge pull request #5630 from apullin/array-assignment 
ast: Add support for array-to-array assignment
 2026-03-05 11:10:12 +00:00
Emil J. Tywoniak 23eb38fe3f celltypes: include newcelltypes to allow legacy code access to migrated yosys_celltypes 2026-03-05 11:59:20 +01:00
Lofty da83c93673 analogdevices: fix SHIFTX name 2026-03-05 05:37:13 +00:00
Lofty f3efa51b3e analogdevices: fix SHREG name 2026-03-05 05:37:13 +00:00
Lofty e2e8245be9 analogdevices: fix MUXF78 name 2026-03-05 05:37:13 +00:00
Lofty c747466a7a analogdevices: update missed T40LP timings 2026-03-05 05:37:13 +00:00
Lofty 91740645a9 analogdevices: update T40LP timings 2026-03-05 05:37:13 +00:00
Lofty 709746b184 analogdevices: update T16FFC timings 2026-03-05 05:37:13 +00:00
Lofty cd60dd4912 synth_analogdevices: update timing model and tests 2026-03-05 05:37:13 +00:00
Lofty 241db706e1 analogdevices: double LUT RAM cost 2026-03-05 05:37:13 +00:00
Lofty 3592d42d3b analogdevices: ignore $assert cells 2026-03-05 05:37:13 +00:00
Krystine Sherwin 5d3ed5a418 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-03-05 05:37:13 +00:00
Krystine Sherwin f06018306d analogdevices: Fixing up bram 
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
 2026-03-05 05:37:13 +00:00
Krystine Sherwin 95ef0cd788 analogdevices: Add BRAM options 
Enable `-force-params`, and tidy up lutram mapping too.
 2026-03-05 05:37:13 +00:00
Lofty 8a09cc5463 analogdevices: LUT RAM only on positive edge 2026-03-05 05:37:13 +00:00
Lofty dea8c275ff analogdevices: DSP tweaks 2026-03-05 05:37:12 +00:00
Lofty 39cb61615f analogdevices: DSP inference 2026-03-05 05:37:12 +00:00
Lofty 891b89f60d analogdevices: remove cells_xtra 2026-03-05 05:37:12 +00:00
Lofty 4954fc980f analogdevices: timings for t40lp 2026-03-05 05:37:12 +00:00
Lofty 2c3876671b analogdevices: use single tech param 2026-03-05 05:37:12 +00:00
Lofty 0a2b6a4f21 analogdevices: expreso does not care about clock buffers 2026-03-05 05:37:12 +00:00
Lofty 6ee0bfa913 analogdevices: prepare for t40lp timings 2026-03-05 05:37:12 +00:00
Krystine Sherwin 9dcffc3dbf analogdevices: Adding RBRAM2 and -tech 2026-03-05 05:37:12 +00:00
Krystine Sherwin 99e26d80b0 analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2026-03-05 05:37:12 +00:00
Krystine Sherwin 9be3cfb3f9 analogdevices: Update lutram.ys test 2026-03-05 05:37:12 +00:00
Krystine Sherwin 376f746bc9 analogdevices: Native LUTRAM primitives 2026-03-05 05:37:12 +00:00
Lofty 30a03886a5 analogdevices: LUTRAM config 2026-03-05 05:37:12 +00:00
Lofty ae5325fe53 analogdevices: update timing model 2026-03-05 05:37:12 +00:00
Lofty c4bec4e8b8 I thought I removed this... 2026-03-05 05:37:12 +00:00
Lofty 85eb07d14d analogdevices: user retargeting 2026-03-05 05:37:12 +00:00
Lofty c9f6d7b2d4 analogdevices: more housekeeping 2026-03-05 05:37:12 +00:00
Lofty f659cbd159 analogdevices: remove some extra cells! 2026-03-05 05:37:12 +00:00
Lofty 6f205b41f5 test suite 2026-03-05 05:37:12 +00:00
Lofty 4f2f064262 synth_analogdevices: remove scopeinfo cells 2026-03-05 05:37:12 +00:00
Lofty d5ea7f7016 Create synth_analogdevices 2026-03-05 05:37:12 +00:00
Lofty 4caffa7ebd
Merge pull request #5725 from yrabbit/disable-wm-2 
GOWIN. Disable read-before-write mode.
 2026-03-05 05:36:28 +00:00
Andrew Pullin 6ac8c8cb05 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-03-04 21:34:40 -08:00
YRabbit 26dc01102e GOWIN. Disable read-before-write mode. 
According to the latest documentation from GOWIN -
"UG285-1.4E Gowin BSRAM & SSRAM User Guide"

The dual port BSRAM of all 55nm devices (including GW1N, GW2A and GW1A
series) does not support the read-before-write mode (WRITE_MODE = 2)

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2026-03-05 09:17:37 +10:00
Emil J 0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
Emil J. Tywoniak 6485a13809 newcelltypes: mark header unstable 2026-03-04 15:17:26 +01:00
Miodrag Milanović 3bc26ff4d0
Merge pull request #5723 from YosysHQ/micko/merge_queue 
CI: add support for merge queue
 2026-03-04 13:18:09 +01:00
nella 16b1a914f1 Aiger use defines for known ops. 2026-03-04 12:39:45 +01:00
nella 04822c6660 Readd builtin_ff_cell_types for plugin parity. 2026-03-04 12:39:45 +01:00
nella b8ee0803ab Remove todo. 2026-03-04 12:39:45 +01:00