2237 Commits

Author	SHA1	Message	Date
Kelvin Chung	7bbdf6049a	Move implementation to constmap and add test	2025-03-26 11:52:55 +00:00
Scott Ashcroft	518986d45c	Make cxxrtl tests work on 32-bit by using __builtin_clzll when needed	2025-03-25 13:12:04 +00:00
Krystine Sherwin	0a1c664f02	simplify: Skip AST_PRIMITIVE in AST_CELLARRAY ... Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error. Add bug4785.ys to tests/verilog to demonstrate.	2025-03-25 12:15:54 +13:00
KrystalDelusion	a647731812	Merge pull request #4677 from YosysHQ/emil/opt_merge-hashing ... opt_merge: hashing performance and correctness	2025-03-25 10:36:02 +13:00
Emil J. Tywoniak	980a0a15c1	stat: allow gzipped liberty files	2025-03-19 13:43:44 +01:00
Anhijkt	5ae32efca5	ice40_dsp: add test	2025-03-15 20:05:57 +02:00
KrystalDelusion	9f1271bee0	Merge pull request #4922 from Anhijkt/fix-splitcells-assert ... splitcells: Fix the assertion bug caused by out-of-bound offset	2025-03-14 16:52:38 +13:00
Krystine Sherwin	8405b3b723	select: Fix -none and -clear ... If the selection stack only has one element (which it normally does), then `design->pop_selection()` automatically resets to the default full selection. This is a problem for `select [-none | -clear]` which were trying to replace the current selection, but because the pop added an extra element when the `execute` returned, the extra selection (the one we actually wanted) gets popped too. So instead, reassign `design->selection()` in the same way as if we called `select [selection]`. Also adds selection stack tests, and removes the accidentally-committed `boxes_dummy.ys`.	2025-03-14 16:32:18 +13:00
Krystine Sherwin	9a9cd05f6c	tests: Fixes for boxes ... cxxrtl `test_unconnected_output` and simple_abc9 `abc9.v` both expect boxed modules in the outputs, so make sure they work as expected.	2025-03-14 14:08:15 +13:00
Krystine Sherwin	061c234559	tests/select: Add tests for selections with boxes	2025-03-14 14:05:40 +13:00
Martin Povišer	6da543a61a	Merge pull request #4818 from povik/macc_v2 ... Add `$macc_v2`	2025-03-12 22:55:40 +01:00
Anhijkt	be3dfdc5ad	splitcells: add tests	2025-03-10 19:41:22 +02:00
Martin Povišer	d8a4991289	Merge pull request #4931 from povik/buf-clean ... opt_clean, simplemap: Add `$buf` handling	2025-03-10 15:10:17 +01:00
Emil J. Tywoniak	33bfc9d19c	opt_merge: test more kinds of cells	2025-03-10 13:14:06 +01:00
Emil J. Tywoniak	ae7a97cc2d	opt_merge: test some unary cells	2025-03-10 13:14:06 +01:00
Emil J. Tywoniak	176faae7c9	opt_merge: fix trivial binary regression	2025-03-10 13:14:06 +01:00
Martin Povišer	557047fe1e	opt_clean, simplemap: Add `$buf` handling	2025-03-07 16:08:38 +01:00
N. Engelhardt	268a034b21	Merge pull request #4866 from YosysHQ/ql_ioff ... add IOFF inference for qlf_k6n10f	2025-03-03 14:12:09 +00:00
Emil J	b4a169527d	Merge pull request #4894 from YosysHQ/emil/abstract ... Add `abstract` pass for formal verification	2025-02-25 11:16:37 +01:00
Emil J. Tywoniak	3f60a2cc67	abstract: test -slice from:to for -init	2025-02-25 00:22:14 +01:00
Emil J. Tywoniak	3cb7054e53	abstract: test -slice for all modes, -rtlilslice for -init	2025-02-25 00:18:16 +01:00
Emil J. Tywoniak	5bd18613bb	abstract: test -init	2025-02-19 23:03:43 +01:00
Emil J. Tywoniak	34e3fcbb31	abstract: test -value	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	d3a90021ad	abstract: test -state	2025-02-18 17:08:45 +01:00
Jannis Harder	7cd822b7f5	rtlil: Add {from,to}_hdl_index methods to Wire ... In the past we had the occasional bug due to some place not handling all 4 combinations of upto/downto and zero/nonzero start_offset correctly.	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	387d0de383	abstract: -state allow partial abstraction, don't use buffer-normalized mode	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	6027030215	abstract: -value MVP, use buffer-normalized mode	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	4637fa74e3	abstract: -init MVP	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	e4ca7b8846	abstract: -state MVP	2025-02-18 17:08:45 +01:00
Krystine Sherwin	db5b76edc1	Add test for shifting by INT_MAX ... Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.	2025-02-14 14:01:27 +13:00
N. Engelhardt	303a386ecc	create duplicate IOFFs if multiple output ports are connected to the same register	2025-01-31 11:28:57 +01:00
Jannis Harder	40c690b030	extract_fa: Add test case	2025-01-30 18:45:06 +01:00
N. Engelhardt	9da4fe747e	fix bus ioff inference	2025-01-28 11:23:36 +01:00
Martin Povišer	916fe998ab	macc_v2: Add test	2025-01-27 13:19:26 +01:00
N. Engelhardt	2241a65f78	fix tests not expecting ioffs	2025-01-24 21:29:10 +01:00
N. Engelhardt	1cf8e7c7db	add ioff inference for qlf_k6n10f	2025-01-24 21:17:15 +01:00
Martin Povišer	c5fd96ebb0	macc_v2: Start new cell	2025-01-24 12:38:03 +01:00
N. Engelhardt	7e3990b681	Merge pull request #4837 from YosysHQ/json_scopinfo_opt ... write_json: add option to include $scopeinfo cells	2025-01-10 09:57:22 +00:00
N. Engelhardt	77b28442a5	emit $scopeinfo cells by default	2025-01-08 14:47:46 +01:00
Martin Povišer	ca0ace66bc	Merge pull request #4817 from povik/macc_v2-1 ... macc: Stop using the B port	2025-01-08 14:42:51 +01:00
N. Engelhardt	dab7905cbe	write_json: add option to include $scopeinfo cells	2025-01-08 13:33:56 +01:00
Martin Povišer	652a1b9806	macc: Stop using the B port ... The B port is for single-bit summands. These can just as well be represented as an additional summand on the A port (which supports summands of arbitrary width). An upcoming `$macc_v2` cell won't be special-casing single-bit summands in any way. In preparation, make the following changes: * remove the `bit_ports` field from the `Macc` helper (instead add any single-bit summands to `ports` next to other summands) * leave `B` empty on cells emitted from `Macc::to_cell`	2025-01-08 13:03:35 +01:00
Martin Povišer	41e4aa8f0a	Merge pull request #4819 from povik/wreduce-resign ... wreduce: Optimize signedness when possible	2025-01-06 15:27:55 +01:00
Emil J	6ab5be4a0e	Merge pull request #4814 from YosysHQ/emil/make-test-fasterer ... test: every test everywhere all at once	2024-12-18 19:02:39 +01:00
Martin Povišer	08778917db	wreduce: Optimize signedness when possible	2024-12-16 12:57:08 +01:00
Emil J. Tywoniak	6240aec433	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
N. Engelhardt	378864d33b	bound attributes: handle vhdl null ranges	2024-12-12 11:42:39 +01:00
Emil J. Tywoniak	603e5eb30a	test: every test everywhere all at once	2024-12-12 01:28:36 +01:00
N. Engelhardt	03033ab6d4	add more tests for bounds attributes, fix attributes appearing in verilog	2024-12-11 16:11:02 +01:00
Martin Povišer	4bd6061709	Merge pull request #4799 from povik/wrapcell-unused ... wrapcell: Optionally track unused outputs	2024-12-10 21:16:28 +01:00
Emil J. Tywoniak	55dcf0e200	tests: fix dfflibmap test - false negative conflict multiple -liberty vs enable inference	2024-12-10 15:48:23 +01:00
Martin Povišer	48c8d70a45	wrapcell: Test `check -assert` post wrapping	2024-12-10 15:13:31 +01:00
Emil J	87736a2bf9	Merge pull request #4807 from YosysHQ/emil/dfflibmap-test-dffe ... dfflibmap: cover enable inference with test	2024-12-10 12:41:11 +01:00
Martin Povišer	b0708a38bf	Merge pull request #4678 from povik/tcl-rtlil-api ... Start Tcl design inspection methods	2024-12-09 15:44:58 +01:00
Emil J. Tywoniak	681b678417	dfflibmap: cover enable inference with test	2024-12-09 14:18:08 +01:00
Miodrag Milanovic	05398889ad	Add verific verilog test cases for blackboxes	2024-12-06 16:13:25 +01:00
N. Engelhardt	8b0f665cc5	add setenv pass	2024-12-06 11:25:43 +01:00
Martin Povišer	d57d21e566	wrapcell: Optionally track unused outputs	2024-12-05 18:16:53 +01:00
Martin Povišer	59a96470df	Merge pull request #4773 from povik/wrapcell ... wrapcell: Add new command	2024-12-04 11:49:51 +01:00
Martin Povišer	14ee5ce800	Merge pull request #4787 from povik/booth-macc ... booth: Map simple `$macc` instances too	2024-12-04 11:49:34 +01:00
Emil J. Tywoniak	6edf9c86cb	libparse: add LibertyMergedCells, enable multiple -liberty args for dfflibmap and clockgate	2024-12-03 17:36:00 +01:00
Emil J	52336369fa	Merge pull request #4783 from YosysHQ/emil/blockrom-driver-conflict ... tests: fix blockrom.v driver conflict	2024-12-03 16:29:43 +01:00
Martin Povišer	109d97bb40	Merge pull request #4706 from povik/keep_hierarchy-adjustalgo ... Adjust `keep_hierarchy` behavior	2024-12-03 12:18:28 +01:00
Martin Povišer	f0704b6ede	Redo integer passing on top of bignum	2024-12-02 19:56:51 +01:00
Emil J. Tywoniak	c26966e3db	tests: fix blockrom.v driver conflict	2024-12-02 16:56:42 +01:00
Emil J. Tywoniak	fe64a714a9	techmap: add a Sklansky option for `$lcu` mapping	2024-12-02 11:34:58 +01:00
Martin Povišer	1ded817beb	booth: Map simple `$macc` instances too	2024-12-01 16:00:04 +01:00
Emil J. Tywoniak	3ebc714dbc	techmap: test consistently with other equiv_make tests	2024-11-29 00:15:02 +01:00
Emil J. Tywoniak	91844968fd	techmap: wrap builtin $lcu as golden module in PPA tests	2024-11-29 00:13:21 +01:00
Emil J. Tywoniak	a41ef0271c	techmap: remove ppa.nomatch by purging internal signals	2024-11-29 00:03:49 +01:00
Emil J. Tywoniak	4bf3677640	techmap: set Han-Carlson adder priority consistent with Kogge-Stone	2024-11-28 23:54:00 +01:00
Emil J. Tywoniak	3f078d9afa	tests: rework Kogge-Stone test consistently with Han-Carlson	2024-11-28 15:33:21 +01:00
Emil J. Tywoniak	1a562f9605	techmap: add TCL test for Han-Carlson adder	2024-11-28 15:33:21 +01:00
Emil J. Tywoniak	289673a807	tests: add support for tcl tests	2024-11-28 15:33:21 +01:00
Martin Povišer	79e9258a31	wrapcell: Add new command	2024-11-27 14:01:00 +01:00
Miodrag Milanović	29e8812bab	Merge pull request #4724 from YosysHQ/micko/blackbox_verific ... verific: fix blackbox regression and add test case	2024-11-25 15:06:54 +01:00
Emil J	5b6baa3ef1	Merge pull request #4744 from YosysHQ/emil/clockgate-liberty ... clockgate: add -liberty	2024-11-20 15:04:00 +01:00
George Rennie	9043dc0ad6	tests: replace read_ilang with read_rtlil ... * #4612 was written before read_ilang was deprecated but merged after so caused test failures. This switches read_ilang to read_rtlil	2024-11-20 14:54:23 +01:00
Emil J	cc17d5bb70	Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width ... opt_demorgan: skip zero width cells	2024-11-20 13:33:16 +01:00
Emil J	18459b4b09	Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width ... opt_reduce: keep at least one input to $reduce_or/and cells	2024-11-20 13:33:04 +01:00
Martin Povišer	7ebe451f9a	Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs ... proc_dff: fix early return bug	2024-11-20 13:26:32 +01:00
Martin Povišer	270846a49a	Merge pull request #4723 from povik/memv2-nordports ... rtlil: Adjust internal check for `$mem_v2` cells	2024-11-18 15:44:39 +01:00
Emil J. Tywoniak	a5bc36f77e	clockgate: add -dont_use	2024-11-18 13:45:30 +01:00
Emil J. Tywoniak	b08441d95c	clockgate: shuffle test liberty to exercise comparison better	2024-11-18 12:48:50 +01:00
Emil J. Tywoniak	1e3f8cc630	clockgate: add test liberty file	2024-11-18 12:45:27 +01:00
Emil J. Tywoniak	c921d85a85	clockgate: fix test comments	2024-11-18 12:33:09 +01:00
Martin Povišer	0d5c412807	read_liberty: s/busses/buses/	2024-11-12 13:33:41 +01:00
Martin Povišer	56a9202a97	Add read_liberty tests of new options	2024-11-12 13:29:16 +01:00
Martin Povišer	5a0cb5d453	Check in filtered samples of IHP's Liberty data for tests	2024-11-12 13:28:15 +01:00
Martin Povišer	1b1a6c4aed	Merge pull request #4525 from georgerennie/peepopt_clock_gate ... peepopt: Add formal opt to rewrite latches to ffs in clock gates	2024-11-11 14:49:09 +01:00
mszelwiga	8e508f2a2a	Fix setting bits of parameters in setundef pass ... This commit also adds test that verifies correctness of this change.	2024-11-08 17:03:08 +01:00
Martin Povišer	e82e5f8b13	rtlil: Adjust internal check for `$mem_v2` cells ... There's a mismatch between what `kernel/mem.cc` emits for memories with no read ports and what the internal RTLIL check expects. The point of dispute it whether some of the parameters relating to read ports have a zero-width value in this case. The `mem.cc` code says no, the internal checker says yes. Surveying the other `$mem_v2` parameters, and internal cell parameters in general, I am inclined to side with the `mem.cc` code. This breaks RTLIL compatibility but for an obscure edge case.	2024-11-08 15:18:43 +01:00
Miodrag Milanovic	df391f5816	verific: fix blackbox regression and add test case	2024-11-08 14:57:04 +01:00
KrystalDelusion	4343c791cb	Merge pull request #4704 from YosysHQ/krys/drop_ilang ... Remove references to ilang	2024-11-08 11:28:06 +13:00
George Rennie	a31c968340	tests/bufnorm: add test for bufnorm of constant	2024-11-07 12:55:50 +01:00
George Rennie	c23e64a236	tests/proc: add proc_dff bug 4712 as testcase	2024-11-07 00:10:17 +01:00
N. Engelhardt	2de9f00368	Merge pull request #4620 from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing	2024-11-06 16:29:07 +01:00
N. Engelhardt	9068ec5566	Merge pull request #4627 from RCoeurjoly/roland/assume_x	2024-11-06 16:27:30 +01:00
Martin Povišer	69a36aec3b	Add keep_hierarchy test	2024-11-05 09:28:45 +01:00
Krystine Sherwin	ee73a91f44	Remove references to ilang	2024-11-05 12:36:31 +13:00
Lofty	3250f2b82b	Merge pull request #4700 from povik/select-list-mod ... Add `select -list-mod`	2024-11-04 15:38:42 +00:00
Martin Povišer	d752ca4847	Fix test after option change	2024-11-04 16:26:46 +01:00
Martin Povišer	f7400a06cd	Fix test	2024-11-04 16:19:59 +01:00
Martin Povišer	23922faecc	Test new Tcl methods	2024-11-04 16:18:50 +01:00
Martin Povišer	c9ed6d8dcf	cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option	2024-11-04 14:28:40 +01:00
Martin Povišer	7aa3fdab80	select: Add `-list-mod` option	2024-11-04 13:16:13 +01:00
Martin Povišer	9432e972f7	Merge pull request #4626 from povik/select-t-at ... select: Add new `t:@<name>` syntax	2024-10-16 10:18:05 +02:00
Emil J. Tywoniak	f9f509bc25	select: add t:@<name> test	2024-10-15 21:06:06 +02:00
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Miodrag Milanović	ecec156965	Merge pull request #4643 from donn/fix_wheels ... wheels: fix missing yosys-abc/share directory	2024-10-09 18:05:58 +02:00
Emil J	038e262332	Merge pull request #4624 from YosysHQ/emil/cxxrtl-smoke-test ... cxxrtl: test stream operator	2024-10-09 05:57:13 -07:00
Mohamed Gaber	3d6b8b8e1a	wheels: fix missing yosys-abc/share directory ... * `misc/__init__.py`: * checks if there's a `yosys-abc` in the same directory - if yes, sets the variable `sys._pyosys_abc` * checks if there's a `share` in the same directory - if yes, sets the variable `sys._pyosys_share_dirname` * `yosys.cc::init_share_dirname`: check for `sys._pyosys_share_dirname`, use it at the highest priority if Python is enabled * `yosys.cc::init_abc_executable_name`: check for `sys._pyosys_abc`, use it at at the highest priority if Python is enabled * `Makefile`: add new target, `share`, to only create the extra targets * `setup.py`: compile libyosys.so, yosys-abc and share, and copy them all as part of the pyosys build * `test/arch/ecp5/add_sub.py`: ported `add_sub.ys` to Python to act as a test for the share directory and abc with Python wheels, used in CI	2024-10-09 13:09:14 +03:00
Martin Povišer	e46cc57cc4	Merge pull request #4613 from povik/err-never-silence ... log: Never silence `log_cmd_error`	2024-10-07 16:12:31 +02:00
Martin Povišer	0aab8b4158	Merge pull request #4605 from povik/liberty-unit-delay ... read_liberty: Optionally import unit delay arcs	2024-10-07 16:11:51 +02:00
Martin Povišer	74e92d10e8	Merge pull request #4593 from povik/aiger2 ... New aiger backend	2024-10-07 16:11:25 +02:00
Martin Povišer	6c1450fdaf	Merge pull request #4607 from povik/ql-nodiv ... quicklogic: Avoid carry chains in division mapping	2024-10-07 16:11:11 +02:00
Martin Povišer	ca5c2fdff1	quicklogic: Relax the LUT number test	2024-10-07 15:27:03 +02:00
Martin Povišer	b01b17689e	Add test of error not getting silenced	2024-10-07 14:49:17 +02:00
Martin Povišer	d0a11e26f3	aiger2: Add test of writing a flattened view	2024-10-07 12:04:33 +02:00
Lofty	13ecbd5c76	quicklogic: test that dividing by a constant does not infer carry chains	2024-10-03 20:05:28 +01:00
Roland Coeurjoly	5ea2c6e6e5	Assume x values for missing signal data in FST ... Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-10-02 12:08:48 +02:00
Emil J. Tywoniak	997cb30f1f	cxxrtl: test stream operator	2024-10-01 13:25:07 +02:00
Roland Coeurjoly	76c615b2ae	Fix: handle VCD variable references with and without whitespace ... Co-authored-by: Miodrag Milanović <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-10-01 11:51:20 +02:00
rherveille	ce7db661a8	Added cast to type support (#4284)	2024-09-29 17:03:01 -04:00
George Rennie	0572f8806f	opt_reduce: add test for constant $reduce_and/or not being zero width	2024-09-25 16:28:41 +01:00
George Rennie	e105cae4a9	opt_demorgan: add test for zero width cell	2024-09-25 16:10:16 +01:00
Martin Povišer	ea765686b6	aiger2: Adjust hierarchy/port handling	2024-09-18 16:55:02 +02:00
Martin Povišer	6c1fa45995	aiger2: Ingest `$pmux`	2024-09-18 16:42:56 +02:00
Martin Povišer	d5756eb9be	tests: Add trivial liberty -unit_delay test	2024-09-18 16:17:03 +02:00
Martin Povišer	31476e89b6	tests: Avoid temporary script file	2024-09-18 16:17:03 +02:00
Martin Povišer	8e29675a23	aiger2: Support `$bwmux`, comparison operators	2024-09-17 13:55:58 +02:00
Martin Povišer	fb26945a20	Start an 'aiger2' backend	2024-09-17 13:55:58 +02:00
Martin Povišer	4cfdb7ab50	Adjust operation naming in aigmap test	2024-09-17 13:55:58 +02:00
Emil J	52382c6544	Merge pull request #4583 from YosysHQ/emil/clock_gate ... clockgate: centralize clock enables out of FFs	2024-09-16 15:41:01 +02:00
N. Engelhardt	c8b42b7d48	Merge pull request #4538 from RCoeurjoly/verific_bounds	2024-09-12 13:04:04 +02:00
Emil J. Tywoniak	1e999a3cb7	clockgate: EN can be a bit on a multi-bit wire	2024-09-11 19:18:25 +02:00
Roland Coeurjoly	bdc43c6592	Add left and right bound properties to wire. Add test. Fix printing ... for signed attributes Co-authored-by: N. Engelhardt <nak@yosyshq.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-09-10 12:52:42 +02:00
Emil J. Tywoniak	7e473299bd	clockgate: bail on constant signals	2024-09-09 21:20:19 +02:00
Emil J. Tywoniak	dc039d8be4	clockgate: test fine-grained cells	2024-09-09 21:03:22 +02:00
Emil J. Tywoniak	e64fceef70	clockgate: prototype clock gating	2024-09-09 15:00:54 +02:00
Miodrag Milanović	b20df72e1e	Merge pull request #4536 from YosysHQ/functional ... Functional Backend	2024-09-06 10:05:04 +02:00
Emily Schmidt	5a476a8d29	functional tests: run from make tests but not smtlib/rkt tests	2024-09-04 10:30:08 +01:00
Krystine Sherwin	7fe9157df2	smtr: Add rkt to functional tests	2024-09-03 11:32:02 +01:00
Miodrag Milanović	598d010349	Merge pull request #4504 from YosysHQ/nanoxplore ... NanoXplore synthesis	2024-09-03 10:19:44 +02:00
Emily Schmidt	2b8db94aa0	functional backend: add test to verify test_generic	2024-08-29 13:14:18 +01:00
George Rennie	8206951f77	proc_dff: add tests	2024-08-28 16:24:47 +01:00
Emily Schmidt	761eff594f	functional backend: missing includes for stl containers	2024-08-22 11:13:58 +01:00
Roland Coeurjoly	91e3773b51	Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting	2024-08-21 14:28:42 +01:00
Emily Schmidt	831da51255	add picorv test to functional backend	2024-08-21 11:04:11 +01:00
Emily Schmidt	99effb6789	add support for initializing registers and memories to the functional backend	2024-08-21 11:03:29 +01:00
Emily Schmidt	145af6f10d	fix memory handling in functional backend, add more error messages and comments for memory edgecases	2024-08-21 11:03:29 +01:00
Emily Schmidt	3cd5f4ed83	add support for RTLIL cells with multiple outputs to the functional backend, implement $fa,$lcu,$alu	2024-08-21 11:03:29 +01:00
Emily Schmidt	c0c90c2c31	functional backend: require shift width == clog2(operand width)	2024-08-21 11:03:29 +01:00
Emily Schmidt	6922633b0b	fix a few bugs in the functional backend and refactor the testing	2024-08-21 11:03:29 +01:00
Emily Schmidt	674e6d201d	rewrite functional backend test code in python	2024-08-21 11:03:29 +01:00
Roland Coeurjoly	80582ed3af	Check the existance of a different set of outputs. No need for (push 1) nor (pop 1)	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	7cff8fa3a3	Fix corner case of pos cell with input and output being same width	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	5780357cd9	Emit valid SMT for stateful designs, fix some cells	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	50f487e08c	Added $ff test	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	762f8dd822	Add readme explaining how to create test files	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	73ed514623	Check that there are not other solutions other than the first given	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	cb5f08364c	´SMT success only if simulation is equivalent	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	e235fc704d	Create std::mt19937 only once	2024-08-21 11:02:31 +01:00
Emily Schmidt	21bb1cf1bc	rewrite functional c++ simulation library	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	39bf4f04f7	Create VCD file from SMT file	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	b98210d8ac	Valid SMT is emitted, improved test script	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	71aaa1c80d	Consolidate tests scripts into one	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	547c5466ec	Ignore smt2 files, generated by the execution of the tests	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	54225b5c42	Add test for SMT backend. Tests if SMT is valid and compares simulation with yosys sim	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	720429b1fd	Add test_cell tests for C++ functional backend	2024-08-21 11:01:09 +01:00
Emil J	e0d3bbf3c3	Merge pull request #4452 from phsauter/shiftadd-underflow-fix ... peepopt: avoid shift-amount underflow	2024-08-19 15:45:46 +02:00
Miodrag Milanovic	54d237ff82	add min_ce_use and min_srst_use parameters	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	dbf1d037e8	Cleanup	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	3848563600	Update tests	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	1a6e5c671f	Add meminit handling for NX_RFB_U	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	40f05009e3	Fix CY chaining and CI injection	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	f4d8ea4c40	Start adding RFB simulation models	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	7e4aef06e4	Add register file mapping	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	41ae513d60	support other I/O configurations	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	34f08bc639	Enable nanoxplore tests	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	a5bfb23b47	start cleaning rams	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	65d2ebac9d	fix test	2024-08-15 17:50:36 +02:00
Lofty	b0c4add642	Added lutram	2024-08-15 17:50:36 +02:00
Lofty	b3f59c9820	Add NX_CY	2024-08-15 17:50:36 +02:00
Lofty	b4e9bb0d85	Add FFs and related tests	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	b4a17cccc3	add few more tests	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	93543bd874	add lut tests	2024-08-15 17:50:36 +02:00
Martin Povišer	c35f5e379c	Extend liberty tests	2024-08-13 18:47:36 +02:00
George Rennie	b6ceff2aab	peepopt clockgateff: add testcase	2024-08-07 10:21:52 +01:00
N. Engelhardt	9f869b265c	Merge pull request #4474 from tony-min-1/mchp ... Add PolarFire FPGA support	2024-07-29 15:28:44 +02:00
Emil J. Tywoniak	01fd72520f	proc_rom: test src attribute on memories	2024-07-29 10:13:45 +02:00
chunlin min	3db69b7a10	inline all tests. Add switch to remove init values as PolarFire DFFs do not support init	2024-07-08 17:03:03 -04:00
Tony Min	d41688f7d7	Revisions (#4) ... * area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>	2024-07-08 10:57:16 -04:00
Tony Min	6fe0e00050	Add missing u sram init (#3) ... add missing INIT for uSRAM	2024-07-04 16:39:10 -04:00
chunlin min	8e7ec2d660	add assertions for synth_microchip tests	2024-07-04 15:45:44 -04:00
chunlin min	e3c4791e5b	move microchip tests from techlibs/microchip/tests to tests/arch/microchip	2024-07-04 14:16:52 -04:00
phsauter	34b5c6d062	peepopt: avoid shift-amount underflow	2024-06-13 23:30:07 +02:00
Marian Buschsieweke	7f89a45ad7	cxxxrtl: fix use of format specifiers in test ... This fix a few instances of incorrect (and non-portable) use of format specifiers.	2024-06-11 07:22:39 +01:00
Asherah Connor	dc69365258	cxxrtl: failing test: unconnected blackbox outputs don't compile.	2024-06-07 14:24:27 +03:00
Martin Povišer	4b67f3757f	Merge pull request #4404 from YosysHQ/povik/bbox_derive ... box_derive: New command to derive modules for boxes	2024-05-31 19:09:18 +02:00
Martin Povišer	97fedff383	box_derive: Tune the test	2024-05-29 20:42:11 +02:00
Martin Povišer	bff2443af8	box_derive: Finish the test	2024-05-21 16:34:49 +02:00
Martin Povišer	c0a196173a	Rename `bbox_derive` to `box_derive`	2024-05-21 16:18:03 +02:00
N. Engelhardt	24f9329c67	Merge pull request #4367 from YosysHQ/lofty/intel_alm-drop-quartus ... intel_alm: drop quartus support	2024-05-21 16:01:23 +02:00
Martin Povišer	557db4ea46	bbox_drive: Add an incomplete test	2024-05-21 14:57:49 +02:00
Martin Povišer	b143e5678f	cellmatch: Rename the special design to `$cellmatch`	2024-05-03 16:42:41 +02:00
Martin Povišer	913bc87c44	cellmatch: Add test	2024-05-03 16:42:41 +02:00
Emil J. Tywoniak	a833f05036	techmap: add dynamic cell type test	2024-05-03 13:53:49 +02:00
Lofty	8cc9aa7fc6	intel_alm: drop quartus support	2024-05-03 11:32:33 +01:00
George Rennie	4e6deb53b6	read_aiger: Fix incorrect read of binary Aiger without outputs ... * Also makes all ascii parsing finish reading lines and adds a small test	2024-04-29 14:06:58 +01:00
N. Engelhardt	e8ec19c273	add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality)	2024-04-12 13:51:06 +02:00
N. Engelhardt	b87327d1b9	fix hierarchy -generate mode handling of cells	2024-04-12 13:38:33 +02:00
Miodrag Milanovic	0c7ac36dcf	Add workflows and CODEOWNERS and fixed gitignore	2024-04-11 14:56:00 +02:00
Martin Povišer	dc746080f5	Merge pull request #4298 from povik/kogge-stone ... techmap: Add a Kogge-Stone option for `$lcu` mapping	2024-04-08 16:46:06 +02:00
N. Engelhardt	8e8885e1cc	Merge pull request #4323 from YosysHQ/tests_update ... Tests update for latest more strict iverilog	2024-04-08 15:10:59 +02:00
Miodrag Milanovic	4ac10040ce	Enable SV for localparam use by Efinix cell_sim	2024-04-08 12:45:43 +02:00
Miodrag Milanovic	91e41d8c80	Move parameters to module declaration	2024-04-08 12:44:37 +02:00
Catherine	d9a4a42389	write_verilog: don't `assign` to a `reg`. ... Fixes #2035.	2024-04-03 13:06:45 +02:00
Merry	d07a55a852	cxxrtl: Fix sdivmod ... x = x.neg(); results in the subsequent x.is_neg() always being false. Ditto for the dividend.is_neg() != divisor.is_neg() test.	2024-03-30 07:56:11 +00:00
Martin Povišer	c49d6e7874	techmap: Add Kogge-Stone test	2024-03-27 11:08:26 +01:00
Martin Povišer	5924d97381	tests: Remove part of test involving combinational loops	2024-03-11 10:45:36 +01:00
Martin Povišer	87e72ef86f	celledges: Add read ports arst paths	2024-03-11 10:45:17 +01:00
Martin Povišer	e4296072c4	check: Rephrase regex for portability	2024-03-11 10:45:17 +01:00
Martin Povišer	e1e77a7fa9	check: Extend testing	2024-03-11 10:45:17 +01:00
Martin Povišer	3eef6450f1	check: Add coarse-grain false positive test	2024-03-11 10:43:49 +01:00
N. Engelhardt	d70113a909	Merge pull request #3972 from nakengelhardt/celledges_shift_ops ... celledges: support shift ops	2024-03-08 09:35:47 +01:00
Jannis Harder	0db76c6ec4	tests/sva: Skip sva tests that use SBY until SBY is compatible again ... This commit is part of a PR that requires corresponding changes in SBY. To prevent CI failures, detect whether those changes already landed and skip the SBY using tests until then.	2024-03-05 14:37:33 +01:00
Roland Coeurjoly	4a2fb18718	Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc	2024-02-25 17:23:56 +01:00
Miodrag Milanović	bc8a3a5b18	Merge pull request #4219 from rovinski/master ... dfflibmap: Add a -dont_use flag to ignore cells	2024-02-20 12:43:44 +01:00
Austin Rovinski	689feed012	dfflibmap: Add a -dont_use flag to ignore cells ... This is an alternative to setting the dont_use property in lib. This brings dfflibmap in parity with the abc pass for dont_use. Signed-off-by: Austin Rovinski <rovinski@nyu.edu>	2024-02-19 13:00:18 -05:00
Martin Povišer	db947e4c71	Merge pull request #4218 from kivikakk/proc_rom-actionless-switch ... proc_rom: don't assert on big actionless switch.	2024-02-19 16:21:40 +01:00
N. Engelhardt	edd154e3cd	Merge pull request #4215 from povik/xprop-race ... Address race in `xprop` tests	2024-02-19 16:16:16 +01:00
Amelia Cuss	bf4a46ccb3	proc_rom: don't assert on big actionless switch. ... See the test case. PROC_ROM will consider this for evaluation, even though -- without any actions -- lhs is empty (but still "uniform"). A zero-width memory is constructed, which later fails check with: ERROR: Assert `width != 0' failed in kernel/mem.cc:518. Ensure we don't proceed if there's nothing to encode.	2024-02-18 01:33:28 +11:00
Jannis Harder	811b7b54d4	Merge pull request #4204 from YosysHQ/micko/gen_test ... do not override existing shell variable	2024-02-16 14:28:56 +01:00
Martin Povišer	e51c77484a	tests: Comment on `A[0]`	2024-02-16 11:43:28 +01:00
Martin Povišer	5a05344d9c	tests: Fix initialization race in xprop tests	2024-02-16 11:43:28 +01:00
Jannis Harder	bbdfcfdf30	clk2fflogic: Fix handling of $check cells ... Fixes a bug in the handling of the recently introduced $check cells. Both $check and $print cells in clk2fflogic are handled by the same code and the existing tests for that were only using $print cells. This missed a bug where the additional A signal of $check cells that is not present on $print cells was dropped due to a typo, rendering $check cells non-functional. Also updates the tests to explicitly cover both cell types such that they would have detected the now fixed bug.	2024-02-14 11:42:27 +01:00
Miodrag Milanovic	353ccc9e58	do not override existing shell variable	2024-02-12 12:58:13 +01:00
Miodrag Milanović	edb95c69a9	Merge pull request #4084 from jix/scopeinfo ... $scopeinfo support	2024-02-12 09:51:22 +01:00
Miodrag Milanovic	10297127be	fix test for verific	2024-02-12 09:19:58 +01:00
Dag Lem	f09ea16bd1	Resolve struct member multiple dimensions defined in stages with typedef	2024-02-11 11:26:52 -05:00
Dag Lem	a4ae773150	Added test for multidimensional packed arrays	2024-02-11 11:26:52 -05:00
Dag Lem	e0d3977e19	Add support for $dimensions and $unpacked_dimensions	2024-02-11 11:26:52 -05:00
Dag Lem	2125357e76	Add support for $increment	2024-02-11 11:26:52 -05:00
Dag Lem	a32d9b6c45	Fix test of memory vs. memory converted to registers ... The purpose of memtest02 in tests/simple/memory.v is to test bit select on both memory (mem1) and memory converted to registers (mem2). After 7cfae2c52, mem1 was automatically converted to registers, and the test no longer worked as intended. This is fixed by adding (* nomem2reg *) to mem1.	2024-02-11 11:26:52 -05:00
Dag Lem	39fea32c6e	Add support for packed multidimensional arrays ... * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges	2024-02-11 11:26:52 -05:00
Thomas Watson	10e06f9b66	tests/various/clk2fflogic_effects.sh: remove /tmp use ... Might not be accessible.	2024-02-10 15:09:54 -06:00
Thomas Watson	b1f8308772	tests/various/clk2fflogic_effects.sh: fix tail invocation ... Previous syntax is a GNU extension and not accepted by macOS. Use documented -n option instead, compatible with POSIX-compliant tail implementations.	2024-02-10 15:07:55 -06:00
Jannis Harder	9288107f43	Test flatten and opt_clean's $scopeinfo handling	2024-02-06 17:51:29 +01:00
Miodrag Milanović	269c50f90e	Merge pull request #4130 from jix/hierarchy-defer-notop ... hierarchy: Without a known top module, derive all deferred modules	2024-02-06 12:08:01 +01:00
Miodrag Milanovic	d00843d436	Add -nordff to test	2024-02-06 10:36:30 +01:00
Jannis Harder	0470cbb00d	hierarchy: Without a known top module, derive all deferred modules ... This fixes hierarchy when used with cell libraries that were loaded with -defer and also makes more of the hierarchy visible to the auto-top heuristic.	2024-02-06 10:31:40 +01:00
Jannis Harder	ffb82df33c	Additional tests for FV $check compatibility	2024-02-02 16:07:10 +01:00
Jannis Harder	e1a59ba80b	async2sync, clk2fflogic: Add support for $check and $print cells	2024-02-01 20:10:39 +01:00
Jannis Harder	331ac5285f	tests: Run async2sync before sat and/or sim to handle $check cells ... Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.	2024-02-01 16:14:11 +01:00
Jannis Harder	2baa578d94	Remove too fragile smtlib2_module test ... This compares the write_smt2 output pretty much verbatim, which contains auto generated private names and fixes an arbitrary ordering. The tested functionality is also covered by SBY tests which actually interpret the write_smt2 output using an SMT solver and thus are much more robust, so we can safely remove this test.	2024-02-01 16:14:11 +01:00
Martin Povišer	ea3dc7c1b4	rtlil: Add wire deletion test	2024-01-29 11:25:54 +01:00
Martin Povišer	08fd47e970	Test roundtripping some processes to Verilog and back	2024-01-24 16:32:25 +00:00
Catherine	fc5ff7a265	cxxrtl: always lazily format print messages. ... This is mostly useful for collecting coverage for the future `$check` cell, where, depending on the flavor, formatting a message may not be wanted even for a failed assertion.	2024-01-19 18:55:23 +00:00
Catherine	b74d33d1b8	fmt: rename TIME to VLOG_TIME. ... The behavior of these format specifiers is highly specific to Verilog (`$time` and `$realtime` are only defined relative to `$timescale`) and may not fit other languages well, if at all. If they choose to use it, it is now clear what they are opting into. This commit also simplifies the CXXRTL code generation for these format specifiers.	2024-01-19 15:12:05 +00:00
Martin Povišer	cb86efa50c	celledges: Add test of shift cells edge data	2024-01-19 11:14:10 +01:00
N. Engelhardt	242ae4ef01	Merge pull request #4135 from YosysHQ/verific_clocking_fix ... Fix verific clocking when no driver exist	2024-01-18 15:40:35 +01:00
Miodrag Milanovic	1764c0ee3c	Fix verific clocking when no driver exist	2024-01-18 08:47:04 +01:00
Catherine	a33acb7cd9	cxxrtl: refactor the formatter and use a closure. ... This commit achieves three roughly equally important goals: 1. To bring the rendering code in kernel/fmt.cc and in cxxrtl.h as close together as possible, with an ideal of only having the bigint library as the difference between the render functions. 2. To make the treatment of `$time` and `$realtime` in CXXRTL closer to the Verilog semantics, at least in the formatting code. 3. To change the code generator so that all of the `$print`-to-`string` conversion code is contained inside of a closure. There are two reasons to aim for goal (3): a. Because output redirection through definition of a global ostream object is neither convenient nor useful for environments where the output is consumed by other code rather than being printed on a terminal. b. Because it may be desirable to, in some cases, ignore the `$print` cells that are present in the netlist based on a runtime decision. This is doubly true for an upcoming `$check` cell implementing assertions, since failing a `$check` would by default cause a crash.	2024-01-16 16:35:51 +00:00
Dag Lem	e0566eafdb	Add test for rhs sign extension in array slice assignment	2024-01-10 21:15:00 +01:00
Dag Lem	dbec704b49	Include x bits in test of lhs dynamic part-select	2024-01-10 20:28:36 +01:00
Dag Lem	a105d2c050	Add torture test for (* nowrshmsk *) stride optimization	2024-01-10 20:28:36 +01:00
Dag Lem	2cab4ff173	Correction and optimization of nowrshmsk ... This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.	2024-01-10 20:28:36 +01:00
Dag Lem	1bbea13f80	Correct hierarchical path names for structs and unions	2024-01-04 17:22:07 +01:00
N. Engelhardt	d87bd7ca3f	Merge pull request #3887 from kivikakk/env-bash ... tests: use /usr/bin/env for bash.	2023-12-18 16:33:35 +01:00
Martin Povišer	449e3dbbd3	cxxrtl: Mask `bmux` result appropriately	2023-12-14 06:57:28 +00:00
Merry	1dff3c83d9	tests/cxxrtl: Add -O2	2023-12-13 12:27:06 +00:00
Merry	29e0cc6acd	cxxrtl: Add simple fuzzing tests for value	2023-12-13 12:21:44 +00:00
Merry	d7cb6981b5	cxxrtl: Fix value::ctlz	2023-12-13 12:21:44 +00:00
Merry	ded63bedd5	cxxrtl: Fix value::sshr	2023-12-13 12:11:57 +00:00
Merry	ff53f3d2b6	cxxrtl: Fix value::shl	2023-12-13 12:02:30 +00:00
Jannis Harder	7b74caa5db	peepopt: Fix padding for the peepopt_shiftmul_right pattern ... The previous version could easily generate a large amount of padding when the constant factor was significantly larger than the width of the shift data input. This could lead to huge amounts of logic being generated before then being optimized away at a huge performance and memory cost. Additionally and more critically, when the input width was not a multiple of the constant factor, the input data was padded with 'x bits to such a multiple before interspersing the 'x padding needed to align the selectable windows to power-of-two offsets. Such a final padding would not be correct for shifts besides $shiftx, and the previous version did attempt to remove that final padding at the end so that the native zero/sign/x-extension behavior of the shift cell would be used, but since the last selectable window also got power-of-two padding appended after the padding the code is trying to remove got added, it did not actually fully remove it in some cases. I changed the code to only add 'x padding between selectable windows, leaving the last selectable window unpadded. This omits the need to add final padding to a multiple of the constant factor in the first place. In turn, that means the only 'x bits added are actually impossible to select. As a side effect no padding is added when the constant factor is equal to or larger than the width of the shift data input, also solving the reported performance bug. This fixes #4056	2023-12-06 18:35:44 +01:00
Martin Povišer	22cc4aff51	quicklogic: Test TDP36K inference with initial data	2023-12-04 15:52:03 +01:00
Krystine Sherwin	e5c32f399a	synth_quicklogic: Testing double_sync_ram_tdp	2023-12-04 15:52:03 +01:00
Krystine Sherwin	97354782c0	Adding double_sync_ram_tdp to blockram.v	2023-12-04 15:52:03 +01:00
Krystine Sherwin	215a777eb3	qlf_tests: minor adjustment ... Renamed python script so that it sits next to the testbench file when alphabetically sorted. Reverted `MAX_WIDTH` to full precision for truncation testing.	2023-12-04 15:52:03 +01:00
N. Engelhardt	33ca6994b7	remove example test	2023-12-04 15:52:03 +01:00
N. Engelhardt	3c5b0ab164	fix test setup for synth_quicklogic memory tests	2023-12-04 15:52:03 +01:00
Krystine Sherwin	509d176523	attempting to sim split memory tests ... and failing	2023-12-04 15:52:03 +01:00
Krystine Sherwin	0d1668c1ee	QLF_TDP36K: asymmetric simulation tests	2023-12-04 15:52:03 +01:00
Krystine Sherwin	497cd021af	QLF_TDP36K: truncation tests matter ... Expected values are now stored in full precision rather than truncating to the same value as the input. i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.	2023-12-04 15:52:03 +01:00
Krystine Sherwin	7f12d0ba95	QLF_TDP36K: more basic tdp/sdp sim tests ... Adds TDP submodule to generator. Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).	2023-12-04 15:52:03 +01:00
Krystine Sherwin	3d08ed216d	QLF_TDP36K: parameterised sim test gen ... Also limited to 16 tests per file to allow parallelism. Previous tests are converted to new test format with no sim test steps.	2023-12-04 15:52:03 +01:00
Krystine Sherwin	ba3be3fd1c	QLF_TDP36K: test bram_tdp post synth	2023-12-04 15:52:03 +01:00
N. Engelhardt	f9c8978128	add example memory test	2023-12-04 15:52:03 +01:00
Krystine Sherwin	ede4eaeee2	quicklogic: wildcard asymmetric memory tests	2023-12-04 15:52:03 +01:00
Krystine Sherwin	8ded7020f4	tests: asymmetric sync rams now correctly asymmetric ... Also both use the same named parameters for better mirroring.	2023-12-04 15:52:03 +01:00
Krystine Sherwin	ba09866217	quicklogic: testing port widths on split rams	2023-12-04 15:52:03 +01:00
Krystine Sherwin	1a843b2a86	quicklogic: testing 1:4 assymetric memory	2023-12-04 15:52:03 +01:00
Krystine Sherwin	7513bfcbfe	quicklogic: fix double width read	2023-12-04 15:52:03 +01:00
Krystine Sherwin	8d3b238b9b	quicklogic: Testing split TDP36K ... Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories. Refactor python blockram template to take a list of params to support the above. Also change the smaller single TDP36K tests to also test `port_a_width` value.	2023-12-04 15:52:03 +01:00
Krystine Sherwin	991850e1c9	quicklogic: Initial blockram tests ... Use python script to generate tests for both SDP and TDP across multiple sizes of RAM. Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.	2023-12-04 15:52:03 +01:00
Martin Povišer	a5c8d246f7	quicklogic: Add k6n10f DSP test	2023-12-04 15:52:03 +01:00
Martin Povišer	db9e5b4f14	quicklogic: Fix `dffs.ys` test	2023-12-04 15:52:03 +01:00
Martin Povišer	554d8caef7	quicklogic: Add basic k6n10f tests	2023-12-04 15:52:03 +01:00