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2367 Commits

Author SHA1 Message Date
Emil J. Tywoniak ddf3c6c8b7 blif: add -gatesi test 2026-01-14 21:41:56 +01:00
nella 763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string 
Add rtlil string getters
 2026-01-14 19:00:47 +01:00
nella 210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Emil J 5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire 
Add autowires in genblk/for expension
 2026-01-13 16:40:22 +01:00
nella b332279baf
Merge pull request #5592 from YosysHQ/gus/5503-yw-load-error-msg 
More helpful error messages when loading Yosys Witness files with `yosys-smtbmc`
 2026-01-13 12:00:06 +01:00
Emil J cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux 
add lut2bmux
 2026-01-12 16:09:13 +01:00
Robert O'Callahan 41a098172d Expect an error from the bug5574.ys test 2026-01-08 09:58:01 +01:00
Roland Coeurjoly f1fc704c84 abc: handle ABC script errors instead of hanging 2026-01-07 23:46:33 +01:00
Krystine Sherwin 9a09758f56
Test empty switches 2026-01-07 13:21:33 +13:00
Gus Smith 9f77465170 Add test 2026-01-06 16:19:04 -08:00
Emil J 0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00
Emil J 2e1a2cfacb
Merge pull request #5561 from YosysHQ/emil/opt_expr-test-avoid-multiple-drivers 
opt_expr: avoid multiple drivers in test
 2026-01-06 14:54:55 +01:00
Natalia 11b0e7ad92 add lut2bmux 2026-01-06 14:48:16 +01:00
Miodrag Milanović d523c88c3c
Merge pull request #5573 from rocallahan/increase-timeout 
Increase test timeout to 10 seconds
 2025-12-29 12:38:34 +01:00
Robert O'Callahan 99d7ab9c42 Increase test timeout to 10 seconds 
On my machine, this test regularly times out when doing "make -j" (which defaults to 128).
The high degree of parallelism seems to slow down the spwaning of ABC processes.
 2025-12-29 04:35:05 +00:00
Natalia 721b504479 lut2mux: add -word option and test 2025-12-23 05:57:40 -08:00
Robert O'Callahan 9ee51c8f27 Add AFL++ Grammar-Generator grammar for RTLIL fuzzing, and instructions for how to use it. 2025-12-22 21:56:26 +00:00
Robert O'Callahan 914e14946d Implement design_equal command 2025-12-21 21:47:40 +00:00
Emil J. Tywoniak 856d455065 opt_expr: avoid multiple drivers issue #4792 in combined assign tests 2025-12-19 18:32:56 +01:00
Emil J. Tywoniak 772d821fb0 opt_expr: reindent test 2025-12-19 18:32:56 +01:00
N. Engelhardt 45d654e2d7 avoid merging formal properties 2025-12-17 20:25:24 +01:00
Miodrag Milanović d861a26e49
Merge pull request #5504 from nataliakokoromyti/verific-run-test-bugfix 
Fix Verific run-test.sh
 2025-12-17 11:08:44 +01:00
nataliakokoromyti 2ded4bd893
Update run-test.sh 
fix: preserve newline at eof
 2025-12-16 04:16:03 -08:00
Krystine Sherwin c69be9d767
Missed an iverilog 
Should now still report an iverilog issue if `iverilog` doesn't exist.
 2025-12-15 10:31:17 +13:00
Krystine Sherwin 24f4902156
Don't mention iverilog if the error wasn't from iverilog 2025-12-15 10:17:19 +13:00
Emil J f003eca615
Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order 
cellaigs: fix function argument evaluation order
 2025-12-12 10:00:09 +01:00
Krystine Sherwin 4da0c552dd
tests/aiger: Fix pipe hiding diff exit status 2025-12-12 11:26:24 +13:00
Yannick Lamarre 54b278d574 Add tests for implicit wires in generate blocks. 
Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com>
 2025-12-10 14:43:42 +01:00
Emil J e08e9119ee
Merge pull request #5516 from rocallahan/limit-threads 
Limit thread usage in tests
 2025-12-10 13:45:07 +01:00
Emil J 46fbed6e6f
Merge pull request #5525 from YosysHQ/emil/fix-xaiger2-empty-cell-input 
aiger2: fix empty cell input
 2025-12-04 16:47:53 +01:00
Robert O'Callahan 2ca28d964b Limit YOSYS_MAX_THREADS to 4 for abcopt-tests 2025-12-04 12:09:49 +01:00
Robert O'Callahan a871415abf Limit YOSYS_MAX_THREADS to 4 when running seed-tests 2025-12-04 12:09:48 +01:00
Robert O'Callahan fc951a28d3 Limit YOSYS_MAX_THREADS to 4 when running makefile-tests so we don't overload systems when running 'make -j... test' 2025-12-04 12:09:04 +01:00
Gus Smith 07a690570e
Merge pull request #5128 from gussmith23/gussmith23-rosette-backend-updates 
Add association-list-based helper functions into Rosette backend
 2025-12-02 16:27:05 -08:00
Emil J. Tywoniak 36f0e0392f aiger2: add crash test 2025-12-02 15:30:02 +01:00
Krystine Sherwin b2e527c67e
tests/aiger: Only write aigmap.err on error 2025-12-02 14:17:16 +13:00
Krystine Sherwin 6842003e76
tests/aiger: Add gold .aag files 
Generated with changes from 26f2c111
 2025-12-02 14:03:37 +13:00
Krystine Sherwin e2e7922756
tests/aiger: Compare .aag outputs against known 
Any files that differ (e.g. due to compiler order of operations changing) will trigger an error.
 2025-12-02 14:03:36 +13:00
Emil J 9871e9b17e
Merge pull request #5496 from YosysHQ/emil/liberty-flop-loops 
read_liberty: support loopy retention cells
 2025-12-01 22:50:20 +01:00
Gus Smith 38ee4fc730 Undo more unnecessary changes 2025-11-29 16:17:27 -08:00
Gus Smith 62e666c2ed Make run-test work from anywhere 2025-11-29 16:08:42 -08:00
Gus Smith fb8a1ad3bc Add back param 2025-11-29 16:07:18 -08:00
Gus Smith 0f8e1e3bf7 Undo more changes 2025-11-29 16:06:18 -08:00
Gus Smith 5f84b8b339 Undo some other changes 2025-11-29 15:32:19 -08:00
Gus Smith e223087578 Undo more changes that slipped in from somewhere? a merge maybe? 2025-11-29 15:28:34 -08:00
Gus Smith 5d5a7ab443 remove unused 2025-11-29 15:08:57 -08:00
Gus Smith 473edd19ed Undo formatting 2025-11-29 15:06:46 -08:00
Gus Smith 403740428c Remove unknown change 2025-11-29 15:01:17 -08:00
Gus Smith 6fe35fa46c Merge remote-tracking branch 'origin/main' into gussmith23-rosette-backend-updates 2025-11-29 14:20:36 -08:00
Natalia d4e0437cfd Fix Verific run-test.mk setup 2025-11-24 15:56:28 -08:00
Krystine Sherwin a8e8746fc0
tests: Tidy up bug3515 
Add base case where mapping is possible for sanity checking.
 2025-11-25 07:35:19 +13:00
Krystine Sherwin ba31a02578
tests: Add bug3515 2025-11-25 07:04:34 +13:00
Krystine Sherwin 44ab884b06 bug5495.sh: Skip test if timeout isn't available 2025-11-21 04:03:39 +00:00
Krystine Sherwin 4d1b688717
Tests: Add testcase for problematic ABC DONE check 2025-11-21 14:46:01 +13:00
Emil J. Tywoniak bfc957ee2d filterlib, read_liberty: add loopy retention cell formal equivalence test 2025-11-21 00:57:54 +01:00
Emil J. Tywoniak b3112bf025 filterlib: prefer using precedence over unsynthesizable verilog 2025-11-21 00:43:54 +01:00
Miodrag Milanović e83d721cb0
Merge pull request #5492 from donn/getitem 
pyosys: __getitem__ for supported classes
 2025-11-19 17:58:01 +01:00
Mohamed Gaber 58e831486d
pyosys: __getitem__ for supported classes 
- functions that have a const `[]` operator method now support `__getitem__` in Python
- fields of a pointer type now return a `reference_internal` instead of a `copy` because classes referenced to by pointers typically aren't copyable (e.g. RTLIL::Wire, RTLIL::Module, etc)
- removed duplicate of test_script.py
 2025-11-19 18:09:41 +02:00
Emil J. Tywoniak 920f4793fb sdc: error on unknown getters 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 07de7509bf sdc: add -keep_hierarchy test 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak dc48ceadd9 sdc: collect strictly matching objects 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak c26aa3186d sdc: collect design objects 2025-11-19 15:25:24 +01:00
Miodrag Milanovic 58d4e2c38e ignore generated file 2025-11-17 13:35:38 +01:00
Robert O'Callahan b870693393 Fix reset_auto_counter_id to correctly detect _NNN_ patterns 
This fixes a regression caused by commit c4c389fdd7.
 2025-11-17 09:21:59 +00:00
Miodrag Milanović 4bfdc62f65
Merge pull request #5472 from Anhijkt/arst-fsm-handling 
fsm_detect: add adff detection
 2025-11-14 13:47:08 +01:00
Anhijkt b08195a9cf typo 2025-11-14 13:34:58 +02:00
Anhijkt a75b999f13 fsm_detect: fix test 2025-11-14 13:25:51 +02:00
Emil J. Tywoniak ae281720cf tests: remove unstable FPGA synthesis result checks 2025-11-12 11:52:04 +01:00
Robert O'Callahan df8444c5e7 Optimize IdString operations to avoid calling c_str() 2025-11-12 11:52:04 +01:00
Robert O'Callahan e95ed7bbab Make NEW_ID create IDs whose string allocation is delayed 2025-11-12 11:52:04 +01:00
Robert O'Callahan 54bde15329 Implement IdString garbage collection instead of refcounting. 2025-11-12 11:52:04 +01:00
KrystalDelusion 529886f7fb
Merge pull request #5473 from YosysHQ/krys/unsized_params 
Handle unsized params
 2025-11-12 07:14:44 +13:00
Rahul Bhagwat 224109151d
add specific package imports and tests 2025-11-08 23:05:10 +05:30
Krystine Sherwin 7302bf9a66
Add CONST_FLAG_UNSIZED 
In order to support unsized constants being used as parameters, the `const` struct needs to know if it is unsized (so that the parameter can be used to set the size).
Add unsized flag to param value serialization and rtlil back-/front-end.
Add cell params to `tests/rtlil/everything.v`.
 2025-11-07 17:45:07 +13:00
Krystine Sherwin e4c5900acd
tests/verilog: Unsized params in cell 
Non-zero case fails with `read_verilog`, but passes with `verific` and `read_slang`.
 2025-11-07 17:13:12 +13:00
Krystine Sherwin a5cc905184
simplify.cc: Fix unsized const in params 2025-11-07 15:52:24 +13:00
KrystalDelusion 24b69cabaa
Merge pull request #5422 from YosysHQ/krys/SVI_support 
Catch partial support of SVI
 2025-11-07 11:16:07 +13:00
Anhijkt 7d10a72490 fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
Emil J a16fc9b4f3
Merge pull request #5467 from YosysHQ/emil/liberty-unquoted-expressions 
libparse: support unquoted expressions
 2025-11-06 19:45:17 +01:00
Emil J. Tywoniak 2bf7aac9d1 Makefile: clean unit test on clean, ensure prepared to fix parallelism 2025-11-06 13:59:14 +01:00
Emil J a2aeef6c96
Merge pull request #5461 from rocallahan/reset-abc-config 
Fix regression in configuring ABC techmapping
 2025-11-06 11:58:04 +01:00
Robert O'Callahan 0f770285f3 Move global ABC configuration variables into AbcConfig and initialize them properly 2025-11-05 13:56:04 +00:00
Martin Povišer 45bb5c690d
Merge pull request #5460 from povik/timeest-comb 
timeest: Add top ports launching/sampling
 2025-11-05 14:29:34 +01:00
Emil J. Tywoniak 90553267b0 libparse: fix quoting and negedge in filterlib -verilogsim 2025-11-05 14:13:58 +01:00
Emil J. Tywoniak b0a3d6a3e7 libparse: fix up tests since liberty expression parsing now normalizes the form of these expressions 2025-11-05 13:06:12 +01:00
Emil J. Tywoniak 4fac7a1b20 libparse: fix space before closing paren in expressions 2025-11-05 13:05:56 +01:00
KrystalDelusion 52c108cd6a
Merge pull request #4596 from YosysHQ/emil/path-sep-refactor 
Refactor getting dirs and filenames from paths to files
 2025-11-05 09:12:54 +13:00
Miodrag Milanović 0751b74e7a
Merge pull request #5441 from donn/pyosys_bugfixes 
pyosys: fix a number of regressions from 0.58
 2025-11-04 07:36:25 +01:00
Krystine Sherwin 1a80c26bae
tests: Fix for macos 
Drop non standard `-t` flag for putting the destination directory first.
 2025-11-04 11:11:01 +13:00
Martin Povišer 5fa7feccd3 timeest: Add top ports launching/sampling 2025-11-03 14:21:28 +01:00
Miodrag Milanović d0a41d4f58
Merge pull request #5442 from rocallahan/verific-bus-ports 
Set `port_id` for Verific `PortBus` wires
 2025-11-03 10:04:07 +01:00
Emil J. Tywoniak b2fe335b2d dfflibmap: fix next_state inversion propagation for DFF flops by inverting reset value polarity 2025-10-28 13:56:28 +01:00
Mohamed Gaber d6b9158fa3
pyosys: fix regressions from 0.58 
- consistently use value semantics for objects passed along FFI boundary
  (not ideal but matches previous behavior)
- add new overload of RTLIL::Module: addMemory that does not require a "donor" object
  - the idea is `Module`, `Memory`, `Wire`, `Cell` and `Process` cannot be directly constructed in Python and can only be added to the existing memory hierarchy in `Design` using the `add` methods - `Memory` requiring a donor object was the odd one out here
- fix superclass member wrapping only looking at direct superclass for inheritance instead of recursively checking superclasses
- fix superclass member wrapping not using superclass's denylists
- fix Design's `__str__` function not returning a string
- fix the generator crashing if there's any `std::function` in a header
- misc: add a crude `__repr__` based on `__str__`
 2025-10-26 02:21:40 +03:00
Robert O'Callahan 25aafab86b Set `port_id` for Verific PortBus wires 2025-10-23 20:51:53 +00:00
Jannis Harder 6a0ee6e4fb Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
Miodrag Milanovic f11a61b32b sim: Make cycle width small as possible and configurable 2025-10-16 11:37:44 +02:00
Miodrag Milanović 759996b968
Merge pull request #5427 from donn/plugin_search_paths 
plugins: add search paths
 2025-10-15 20:02:05 +02:00
Emil J 9d21585a4c
Merge pull request #5426 from rocallahan/parse-sigspec 
Don't stop parsing sigspec after a {} group.
 2025-10-15 17:31:11 +02:00
Mohamed Gaber e86797f029
plugins: add search path 
This uses the environment variable `YOSYS_PLUGIN_PATH` to provide multiple colon-delimited search paths for native plugins in a similar manner to `PATH` for executables and `PYTHONPATH` for Python modules.

This addresses https://github.com/YosysHQ/yosys/issues/2545, allowing Yosys to be better packaged in non-FHS environments such as Nix.
 2025-10-15 14:13:25 +03:00