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1932 Commits

Author SHA1 Message Date
Akash Levy 30241e07eb Fix segfault 2024-07-03 02:29:48 -07:00
Akash Levy fcd073ab51 Smallfix 2024-07-02 15:13:58 -07:00
Akash Levy 0596766cbd Merge upstream yosys changes 2024-07-01 18:33:38 -07:00
Akash Levy dec43679be See if this fixes issues on Innatera design 2024-06-28 03:13:38 -07:00
gatecat 22d8df1e7e liberty: Support for IO liberty files for verification 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-06-19 21:12:42 +02:00
Akash Levy 719bbd7523 Improve SCC reporting 2024-06-17 14:18:41 -07:00
Miodrag Milanovic dfde792288 Refactored import code 2024-06-17 14:49:58 +02:00
Miodrag Milanovic 19da7f7d59 Update makefile to make options uniform 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0f3f731254 Handle -work for vhdl, and clean messages 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0a81c8e161 Import all modules from all libraries when when needed 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7c3094633d Compile with hier_tree separate SV and VHDL as well 2024-06-17 13:29:11 +02:00
Miodrag Milanovic e2e189647f Cleanup 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7bec332b68 SV + VHDL with RTL support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 25d50bb2af VHDL only build support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 54bf9ccf06 Add initial support for Verific without additional YosysHQ patch 2024-06-17 13:29:11 +02:00
Akash Levy a0c0384683 Preserve instances 2024-06-16 20:20:10 -07:00
Akash Levy e23e33441f Update yosys from upstream 2024-06-15 14:23:24 -07:00
Akash Levy fce46d2a53 Add better Yosys/Verific name aliasing and reenable dffe opt 2024-06-15 14:18:33 -07:00
Akash Levy 2337d97977 Sub1 fix 2024-06-13 15:33:17 -07:00
Akash Levy ac0a9e7366 Updates 2024-06-10 20:52:11 -07:00
Akash Levy b9b776d211 Update for no preservation of user nets 2024-06-10 20:33:05 -07:00
Martin Povišer b593f5c01c Update the overview comment in `ast.h` 2024-06-10 16:38:39 +02:00
Akash Levy d930310599 Enable more updates 2024-06-09 13:54:34 -07:00
Mike Inouye b0ab1cf8c3 Fix memory leak in verific file parsing. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-06-07 22:51:28 +00:00
Akash Levy 8499d31cf2 Revert veri_break_loops setting 2024-06-07 00:09:01 -07:00
Akash Levy c8f7441a4a Fix skip default value 2024-06-05 09:33:03 -07:00
Akash Levy c59a997255 Ignore files properly 2024-06-05 07:53:21 -07:00
Akash Levy 4d44099d09 Support for ignoring translate_off and ignoring files 2024-06-05 05:00:05 -07:00
Akash Levy 5dc62bec0b Support .inc files and readmemh missing file 2024-06-03 20:05:30 -07:00
Akash Levy 92e44cc9a3 Minor fix to ignore files 2024-06-03 18:17:50 -07:00
Akash Levy 4339b3681a Elaborate top level modules undo 2024-06-03 16:17:51 -07:00
Akash Levy a692bf17d7 Improper ignore translates 2024-06-03 11:23:16 -07:00
Akash Levy 783c0a593a Actually optimize with Verific now 2024-06-03 04:55:47 -07:00
Akash Levy 4475b50ffa Undo some ugly stuff and make more attempted fixes 2024-06-02 23:33:23 -07:00
Akash Levy 2585636d18 Use ability to get/set IMPORT runtime flags 2024-06-02 22:24:29 -07:00
Akash Levy 28a03380b7 Priority selector fixes (opt order), relaxed checking, warning if using Yosys case statements 2024-06-02 18:45:31 -07:00
Akash Levy 85cbd05bb1 Update some runtime flags to fix some potential issues 2024-06-02 01:12:43 -07:00
Akash Levy 5bc23b272a Add blackboxes a little later and use ignore files rather than ignore modules 2024-05-30 14:17:10 -07:00
Akash Levy 8b93aa10cb Add leakage power unit support 2024-05-29 23:43:47 -07:00
Akash Levy a55a4d461e Infer wide operators pre elaboration (post does not work as well!) 2024-05-28 04:39:29 -07:00
Akash Levy 4062825a9e Disable Liberty support, add blackbox Verilog module, and add attribute parsing into Yosys Liberty parser 2024-05-28 01:47:46 -07:00
Akash Levy b90c20cd14 Update Verific, add opt to hierarchy pass, make opt run a bunch of Verific optimizations, update some Verific runtime flags 2024-05-27 21:56:08 -07:00
Akash Levy a98fcbd48b Revert Verific flags 2024-05-25 23:21:31 -07:00
Akash Levy 60ce37c2bd Don't reenable verific, move to c_cpp_properties.json in .vscode 2024-05-24 01:49:54 -07:00
Akash Levy 22bdf4035a Verific to handle all RAMs 2024-05-24 01:08:37 -07:00
Akash Levy 6300c491ea Update Yosys runtime flags for Verific to remove multi-port memory support 2024-05-24 00:26:37 -07:00
Akash Levy 66eabb1d2c Define SYNTH and OVL_SVA by default 2024-05-23 21:05:57 -07:00
Akash Levy 187737b86a Don't adjust naming on imported cells. Add $ for each pass 2024-05-19 15:02:40 -07:00
Akash Levy 60e598b9c8 Define SYNTHESIS earlier and in both, support ignored module specification 2024-05-17 04:46:28 -07:00
Akash Levy 375f73bbce Update for Amba support 2024-05-15 15:37:14 -07:00
Akash Levy ed42470d45 Move ignore translate up here and update verificc 2024-05-14 16:02:33 -07:00
Akash Levy 81b542fd31 Updated to support Amba comments and .h files 2024-05-14 13:25:43 -07:00
Akash Levy 667c3375e8 Macro defines don't pass or succeed the same way 2024-05-13 15:53:54 -07:00
Akash Levy fb182d10d6 Update formats to include .svh 2024-05-13 00:00:49 -07:00
Akash Levy ba5b12ae0c Don't include source in name 2024-05-11 23:14:39 -07:00
Akash Levy 36f9c50c03 Add mode for nested capital F file 2024-05-11 12:53:33 -07:00
Akash Levy a7e1dcef12 Move register file to after registering directories, also rename to AUTO-DISCOVER 2024-05-10 12:44:36 -07:00
Akash Levy fb55287a3b Add SVP extension, log auto-discovery, support gzip in verific 2024-05-10 11:09:22 -07:00
Akash Levy c7f66737aa Fix Yosys to allow SV again 2024-05-09 06:36:02 -07:00
Akash Levy da8c1955af Updates from YosysHQ 2024-05-09 05:10:44 -07:00
Akash Levy 8841cc4d76 Copy all info from .f file to hdl_file_sort for better auto-discovery 2024-05-09 04:54:57 -07:00
Akash Levy b5af9b9a8a Fix SystemVerilog support for .v files 2024-05-09 04:54:00 -07:00
Miodrag Milanović 1a54e8d47b
Merge pull request #4379 from QuantamHD/fix_verific 
frontend: Fixes verific import around range order
 2024-05-09 11:52:34 +02:00
Ethan Mahintorabi 82a4a87c97
Fixes error with vector indicies of the form [2:7] [-12:7] 
Make sure that we correctly adjust the value to align it to a zero
indexed list with lsb = 0

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 20:29:47 +00:00
Akash Levy 47b6738124 Add -auto_discover to import 2024-05-08 04:21:30 -07:00
Akash Levy 2e21078a83
Merge branch 'YosysHQ:main' into master 2024-05-07 18:21:19 -07:00
Ethan Mahintorabi c039da2ec1
renames variables for more code clairty 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:09:52 +00:00
Ethan Mahintorabi a2c1b268d9
frontend: Fixes verific import around range order 
Test Case
```
module packed_dimensions_range_ordering (
    input  wire [0:4-1] in,
    output wire [4-1:0] out
);
  assign out = in;
endmodule : packed_dimensions_range_ordering

module instanciates_packed_dimensions_range_ordering (
    input  wire [4-1:0] in,
    output wire [4-1:0] out
);
  packed_dimensions_range_ordering U0 (
      .in (in),
      .out(out)
  );
endmodule : instanciates_packed_dimensions_range_ordering
```

```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = { in[0], in[1], in[2], in[3] };
endmodule

// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = in;
endmodule
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:00:06 +00:00
Krystine Sherwin df95ea824b read_verilog: Add missing defaults for flags 
Fix for YosysHQ/sby#103
 2024-05-07 20:25:36 +02:00
Akash Levy 8c330c0e4b
Merge branch 'YosysHQ:main' into master 2024-04-29 22:22:47 -07:00
George Rennie 4e6deb53b6 read_aiger: Fix incorrect read of binary Aiger without outputs 
* Also makes all ascii parsing finish reading lines and adds a small
  test
 2024-04-29 14:06:58 +01:00
Akash Levy 45b723d6f3
Merge branch 'YosysHQ:main' into master 2024-04-25 06:24:57 -07:00
KrystalDelusion c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup 
Typo fixing
 2024-04-25 09:54:48 +12:00
Akash Levy 3945e6ecff
Merge branch 'YosysHQ:main' into master 2024-04-16 10:59:45 -07:00
Miodrag Milanovic af94123730 verific: expose library name as module attribute 2024-04-15 17:01:07 +02:00
Akash Levy 6a3bb58d5d Updates from yosys 2024-04-14 18:53:44 -07:00
N. Engelhardt 3d5e23e585
Merge pull request #4302 from YosysHQ/vhdl_2019 
Verific support for VHDL 2019
 2024-04-09 18:25:05 +02:00
N. Engelhardt 18afa36acd
Merge pull request #4273 from YosysHQ/vhdl_params 
verific: Improve import VHDL constants
 2024-04-09 18:01:41 +02:00
Akash Levy 29e9d3ea92 Updates for hiding verific 2024-04-09 07:16:22 -07:00
akash 840cdb415b Update Verific, add to gitmodules, remove unused/GPL features from Makefile 2024-04-08 12:36:08 -07:00
Akash Levy e3f633fae6
Merge branch 'YosysHQ:main' into master 2024-04-08 12:26:40 -07:00
Catherine a5441bc00c fmt: `FmtPart::{STRING→LITERAL},{CHARACTER→STRING}`. 
Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
 2024-04-02 12:13:22 +02:00
Miodrag Milanovic f536de0e0e Verific support for VHDL 2019 2024-03-28 13:21:55 +01:00
Akash Levy dd35d2da23 Modifications 2024-03-21 11:31:43 -07:00
Miodrag Milanovic 4367e176fb code split and cleanup 2024-03-19 09:15:04 +01:00
Miodrag Milanovic 9eebc80170 handle standard types 2024-03-18 10:35:01 +01:00
Krystine Sherwin 3eeefd23e3
Typo fixup(s) 2024-03-18 11:09:23 +13:00
Miodrag Milanovic 7c09fa572e real number handling and default to string 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 4279cea33a improve handling VHDL constants 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 858eae5572 verific_const: convert VHDL values to RTLIL consts 2024-03-14 10:37:56 +01:00
Martin Povišer b16f4900fd ast/simplify: Interpret hdlname w/o expecting backslash 2024-02-13 21:38:41 +01:00
Catherine d8ce26a5ba read_verilog: correctly format `hdlname` attribute value. 
The leading slash is not a part of the attribute as it only concerns
public values.
 2024-02-13 18:41:53 +00:00
Miodrag Milanovic ae7daf99f4 Verific: Add attributes to module instantiation 2024-02-12 09:53:47 +01:00
Dag Lem f09ea16bd1 Resolve struct member multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem 03f35c3def Resolve multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem e0d3977e19 Add support for $dimensions and $unpacked_dimensions 2024-02-11 11:26:52 -05:00
Dag Lem 2125357e76 Add support for $increment 2024-02-11 11:26:52 -05:00
Dag Lem 88d9e213cb Decoding of a few more AST nodes in dumpVlog 2024-02-11 11:26:52 -05:00
Dag Lem 39fea32c6e Add support for packed multidimensional arrays 
* Generalization of dimensions metadata (also simplifies $size et al.)
* Parsing and elaboration of multidimensional packed ranges
 2024-02-11 11:26:52 -05:00
Catherine 1236bb65b6 read_verilog: don't include empty `opt_sva_label` in span. 
Consider this SystemVerilog file:

    module top(...);
      input clk;
      input [7:0] data;
      input ack;

      always @(posedge clk)
        if (ack) begin
          assert(data != 8'h0a);
        end
    endmodule

Before this commit, the span for the assert was:

        if (ack) begin>
          assert(data != 8'h0a)<;

After this commit, the span for the assert is:

        if (ack) begin
          >assert(data != 8'h0a)<;

This helps editor integrations that only look at the beginning
of the span.
 2024-02-08 14:25:35 +00:00