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1765 Commits

Author SHA1 Message Date
Janeczko Jakub d840a852a9 Fix typo in comment about address collision pattern 2026-08-04 06:44:05 +02:00
Jakub Janeczko 0b0f5cbf26 remove generic path width 2026-08-04 06:44:05 +02:00
Jakub Janeczko 533899ca7e format 2026-08-04 06:44:05 +02:00
Jakub Janeczko a95d626691 cleaner assign with transparency 2026-08-04 06:44:05 +02:00
Jakub Janeczko 2047506440 bypass part width is 1 2026-08-04 06:44:05 +02:00
Jakub Janeczko cf40dfabf5 new transparent memory verilog pattern 2026-08-04 06:44:05 +02:00
Miodrag Milanović 0955fcadab
Merge pull request #5983 from YosysHQ/nak/write_btor_bweqx 
handle $bweqx in btor backend
 2026-08-03 14:34:39 +00:00
Miodrag Milanovic 2cb3d671d6 yosys-witness: give error on justice property, support only 'b' 2026-07-07 12:19:38 +02:00
N. Engelhardt b2fccbb52f handle $bewqx in btor backend 2026-06-23 08:57:09 +02:00
Miodrag Milanovic a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic 48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
KrystalDelusion e20a9168fb
Merge pull request #5971 from YosysHQ/krys/upto_indexing 
write_verilog: Fix upto indexing for single bit
 2026-06-22 23:04:16 +00:00
Miodrag Milanovic ebcbc06951 smtbmc: support latest bitwuzla 2026-06-22 08:40:16 +02:00
Krystine Sherwin 338d4adef2
write_verilog: Fix upto indexing for single bit 2026-06-19 10:18:27 +12:00
nella 5d7486115a
Merge pull request #5887 from YosysHQ/nella/fix-signedness-4402 
Fix: `read_verilog` doesn't respect `signed` keyword
 2026-06-18 16:53:37 +00:00
N. Engelhardt 06201b857e
Merge pull request #5892 from gipsyh/smt2 
smt2: use canonical SMT names in memory metadata
 2026-06-09 12:49:11 +00:00
Miodrag Milanović 78e05dfb00
Merge pull request #5894 from YosysHQ/gcc_16 
Bump CI to gcc-16 and fix warnings
 2026-06-03 12:07:45 +00:00
Emil J 136d80e3d7
Merge pull request #5918 from mikesinouye/keywords 
verilog backend: runtime optimization for keyword pool
 2026-06-03 11:26:20 +00:00
Miodrag Milanovic a599999d1f Fixed warnings found by gcc-16 2026-06-03 13:09:38 +02:00
Catherine a727e7f6e7 Migrate build system to CMake 
See #5895 for details.

This commit does not include CI or documentation changes.
 2026-06-03 08:58:10 +00:00
Mike Inouye a14650d07b verilog backend: runtime optimization for keyword pool 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2026-05-29 17:53:31 +00:00
Yuheng Su caba96515e smt2: use canonical SMT names in memory metadata 2026-05-17 02:27:55 +00:00
Miodrag Milanovic 75dcbe03c6 Convert RTLIL::unescape_id of IdString to unescape() 2026-05-16 19:49:45 +02:00
Miodrag Milanovic 8bbc3c359c Remove id2cstr uses in our code base 2026-05-16 19:49:45 +02:00
Miodrag Milanovic e4a3b44e8e Fixed not intentional log_signal removal 2026-05-15 12:34:54 +02:00
nella 38c2806636 Make sure to apply correct signedness to loop vars. 2026-05-13 16:52:07 +02:00
Codexplorer e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
Lofty ed5d122174
Merge pull request #5793 from YosysHQ/lofty/abc-refactor-4 
read/write_xaiger2: further cleanup [sc-269]
 2026-04-21 12:13:42 +00:00
Lofty f09afcf581 write_xaiger2: further cleanup 2026-04-08 11:08:44 +01:00
Emil J b485173428
Merge pull request #5792 from YosysHQ/emil/toposort-stability 
toposort: avoid run to run variance caused by pointer sensitivity
 2026-04-08 08:51:47 +00:00
Emil J. Tywoniak cd49dc7be8 cxxrtl: stable TopoSort 2026-04-06 15:09:52 +02:00
Lofty b55fd6718b write_xaiger2: fix indentation 2026-04-02 10:47:08 +01:00
Lofty 568a31c83a write_xaiger2: fix function argument evaluation order 2026-03-31 10:40:58 +01:00
Catherine 18d94fe9a4
Merge pull request #5740 from kivikakk/push-utvloulmsuqy 
cxxrtl: Suppress another un/signed comparison warning!
 2026-03-11 10:27:27 +00:00
Asherah Connor 5c74446e57 cxxrtl: Suppress another un/signed comparison warning! 2026-03-11 20:50:09 +11:00
Asherah Connor c5c104f560 cxxrtl: Suppress un/signed comparison warning; this is positive 2026-03-11 18:35:48 +11:00
nella 16b1a914f1 Aiger use defines for known ops. 2026-03-04 12:39:45 +01:00
nella cae54a4c7b Aiger use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak 7a5c303ccd backends: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 665b6eeb4a aiger2: add TODO 2026-03-04 12:22:14 +01:00
KrystalDelusion 1d3f9b7905
Merge pull request #5687 from YosysHQ/nella/pdr-doc 
Update help text for rename -witness and write_aiger -ywmap
 2026-03-02 09:29:25 +13:00
nella 2b4f481850 Cleanup docs. 2026-02-18 09:24:41 +01:00
nella e6e57b33e3 document abc --keep-going pdr [sc-220]. 2026-02-15 09:00:04 +01:00
Gus Smith 7a0774c3bb Don't dump params by default 2026-02-11 08:33:39 -08:00
Gus Smith 1ede98797f Update backends/verilog/verilog_backend.cc 
Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com>
 2026-02-11 08:10:57 -08:00
Gus Smith 9ad7aed4a5 Update backends/verilog/verilog_backend.cc 
Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com>
 2026-02-11 08:10:57 -08:00
Gus Smith 12ace45b89 Support param. default values in JSON FE and SV BE 2026-02-11 08:10:55 -08:00
kamay e0077b188d Add gatesi_mode in BLIF format 2026-01-14 21:41:56 +01:00
nella b332279baf
Merge pull request #5592 from YosysHQ/gus/5503-yw-load-error-msg 
More helpful error messages when loading Yosys Witness files with `yosys-smtbmc`
 2026-01-13 12:00:06 +01:00
Gus Smith 4d237bdd92 Deliver more helpful error messages 2026-01-06 16:19:54 -08:00