mirror of https://github.com/YosysHQ/yosys.git
write_xaiger2: further cleanup
This commit is contained in:
Lofty
parent
a96cf8cc2b
commit
f09afcf581
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@ -21,6 +21,9 @@
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// - gracefully handling inout ports (an error message probably)
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// - undriven wires
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// - zero-width operands
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// - decide how to unify this with cellaigs
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// - break up Index into something smaller
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// - (C++20) remove snprintf-into-std::ostream weirdness
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#include "kernel/register.h"
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#include "kernel/newcelltypes.h"
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@ -179,6 +182,9 @@ struct Index {
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} else {
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// AigMaker::node2index
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// In XAIGER, the ordering of inputs is used to distinguish between AND
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// and XOR gates. AND gates have their first input literal be larger
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// than their second, and vice-versa for XORs.
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if (a < b) std::swap(a, b);
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auto pair = std::make_pair(a, b);
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@ -531,7 +537,7 @@ struct Index {
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Design *design = index.design;
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auto &minfo = leaf_minfo(index);
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if (!minfo.suboffsets.count(cell))
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log_error("Reached unsupport cell %s (%s in %s)\n", log_id(cell->type), log_id(cell), log_id(cell->module));
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log_error("Reached unsupported cell %s (%s in %s)\n", log_id(cell->type), log_id(cell), log_id(cell->module));
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Module *def = design->module(cell->type);
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log_assert(def);
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levels.push_back(Level(index.modules.at(def), cell));
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@ -550,13 +556,13 @@ struct Index {
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{
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std::string ret;
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bool first = true;
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for (auto pair : levels) {
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for (auto [minfo, cell] : levels) {
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if (!first)
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ret += ".";
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if (!pair.second)
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ret += RTLIL::unescape_id(pair.first.module->name);
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if (!cell)
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ret += RTLIL::unescape_id(minfo.module->name);
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else
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ret += RTLIL::unescape_id(pair.second->name);
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ret += RTLIL::unescape_id(cell->name);
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first = false;
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}
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return ret;
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@ -565,8 +571,8 @@ struct Index {
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int hash() const
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{
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int hash = 0;
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for (auto pair : levels)
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hash += (uintptr_t) pair.second;
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for (auto [_, cell] : levels)
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hash += (uintptr_t) cell;
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return hash;
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}
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@ -575,9 +581,12 @@ struct Index {
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if (levels.size() != other.levels.size())
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return false;
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for (int i = 0; i < levels.size(); i++)
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if (levels[i].second != other.levels[i].second)
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for (int i = 0; i < levels.size(); i++) {
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auto* cell = levels[i].second;
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auto* other_cell = other.levels[i].second;
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if (cell != other_cell)
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return false;
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}
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return true;
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}
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@ -740,6 +749,9 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
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nands++;
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lit_counter += 2;
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// In XAIGER, the ordering of inputs is used to distinguish between AND
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// and XOR gates. AND gates have their first input literal be larger
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// than their second, and vice-versa for XORs.
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if (a < b) std::swap(a, b);
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encode(out - a);
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encode(a - b);
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@ -756,7 +768,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
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log_assert(lit_counter == (Lit) (ninputs + nlatches + nands) * 2 + 2);
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char buf[128];
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snprintf(buf, sizeof(buf) - 1, "aig %08d %08d %08d %08d %08d\n",
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snprintf(buf, sizeof(buf), "aig %08d %08d %08d %08d %08d\n",
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ninputs + nlatches + nands, ninputs, nlatches, noutputs, nands);
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f->write(buf, strlen(buf));
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}
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@ -773,8 +785,9 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
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log_assert(w);
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if (w->port_input && !w->port_output)
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for (int i = 0; i < w->width; i++) {
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pi_literal(SigBit(w, i)) = lit_counter;
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inputs.push_back(SigBit(w, i));
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auto bit = SigBit(w, i);
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pi_literal(bit) = lit_counter;
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inputs.push_back(bit);
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lit_counter += 2;
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ninputs++;
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}
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@ -791,7 +804,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
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for (auto bit : SigSpec(w)) {
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(void) bit;
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char buf[16];
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snprintf(buf, sizeof(buf) - 1, "%08d\n", 0);
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snprintf(buf, sizeof(buf), "%08d\n", 0);
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f->write(buf, strlen(buf));
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noutputs++;
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}
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@ -804,16 +817,19 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
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for (auto w : top->wires())
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if (w->port_output) {
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for (auto bit : SigSpec(w))
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// Each call to eval_po eventually reaches emit_gate and
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// encode which writes to f.
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outputs.push_back({bit, eval_po(bit)});
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}
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auto data_end = f->tellp();
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// revisit header and the list of outputs
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f->seekp(file_start);
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write_header();
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for (auto pair : outputs) {
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for (auto [_, po] : outputs) {
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char buf[16];
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snprintf(buf, sizeof(buf) - 1, "%08d\n", pair.second);
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snprintf(buf, sizeof(buf), "%08d\n", po);
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f->write(buf, strlen(buf));
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}
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// double check we arrived at the same offset for the
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@ -822,12 +838,13 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
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f->seekp(data_end);
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int i = 0;
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for (auto pair : outputs) {
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if (SigSpec(pair.first).is_wire()) {
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for (auto [bit, _] : outputs) {
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if (SigSpec(bit).is_wire()) {
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// primary output symbol
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char buf[32];
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snprintf(buf, sizeof(buf) - 1, "o%d ", i);
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snprintf(buf, sizeof(buf), "o%d ", i);
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f->write(buf, strlen(buf));
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std::string name = RTLIL::unescape_id(pair.first.wire->name);
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std::string name = RTLIL::unescape_id(bit.wire->name);
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f->write(name.data(), name.size());
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f->put('\n');
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}
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@ -836,8 +853,9 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
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i = 0;
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for (auto bit : inputs) {
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if (SigSpec(bit).is_wire()) {
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// primary input symbol
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char buf[32];
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snprintf(buf, sizeof(buf) - 1, "i%d ", i);
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snprintf(buf, sizeof(buf), "i%d ", i);
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f->write(buf, strlen(buf));
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std::string name = RTLIL::unescape_id(bit.wire->name);
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f->write(name.data(), name.size());
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@ -1242,29 +1260,29 @@ struct XAigerWriter : AigerWriter {
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reset_counters();
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for (auto w : top->wires())
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if (w->port_input && !w->port_output)
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for (int i = 0; i < w->width; i++)
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ensure_pi(SigBit(w, i));
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if (w->port_input && !w->port_output)
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for (int i = 0; i < w->width; i++)
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ensure_pi(SigBit(w, i));
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int proper_po_num = 0;
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for (auto w : top->wires())
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if (w->port_output)
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proper_po_num += w->width;
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if (w->port_output)
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proper_po_num += w->width;
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prep_boxes(proper_po_num);
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for (auto w : top->wires())
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if (w->port_output)
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for (int i = 0; i < w->width; i++) {
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// When a module output is directly driven by an opaque box, we
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// don't emit it to the mapping file to aid re-integration, but we
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// do emit a proper PO.
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if (map_file.is_open() && !driven_by_opaque_box.count(SigBit(w, i))) {
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map_file << "po " << proper_pos_counter << " " << i
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<< " " << w->name.c_str() << "\n";
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}
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proper_pos_counter++;
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pos.push_back(std::make_pair(SigBit(w, i), HierCursor{}));
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}
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if (w->port_output)
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for (int i = 0; i < w->width; i++) {
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// When a module output is directly driven by an opaque box, we
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// don't emit it to the mapping file to aid re-integration, but we
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// do emit a proper PO.
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if (map_file.is_open() && !driven_by_opaque_box.count(SigBit(w, i))) {
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map_file << "po " << proper_pos_counter << " " << i
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<< " " << w->name.c_str() << "\n";
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}
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proper_pos_counter++;
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pos.push_back(std::make_pair(SigBit(w, i), HierCursor{}));
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}
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this->f = f;
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// start with the header
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@ -1274,7 +1292,7 @@ struct XAigerWriter : AigerWriter {
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// insert padding where output literals will go (once known)
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for (auto _ : pos) {
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char buf[16];
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snprintf(buf, sizeof(buf) - 1, "%08d\n", 0);
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snprintf(buf, sizeof(buf), "%08d\n", 0);
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f->write(buf, strlen(buf));
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}
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auto data_start = f->tellp();
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@ -1291,35 +1309,36 @@ struct XAigerWriter : AigerWriter {
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write_header();
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for (auto lit : outlits) {
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char buf[16];
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snprintf(buf, sizeof(buf) - 1, "%08d\n", lit);
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snprintf(buf, sizeof(buf), "%08d\n", lit);
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f->write(buf, strlen(buf));
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}
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// double check we arrived at the same offset for the
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// main data section
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log_assert(data_start == f->tellp());
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// extensions
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// XAIGER extensions
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f->seekp(0, std::ios::end);
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f->put('c');
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f->put('c'); // 'c': comment (marks beginning of extensions)
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// insert empty 'r' and 's' sections (abc crashes if we provide 'a' without those)
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f->put('r');
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write_be32(*f, 4);
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write_be32(*f, 0);
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f->put('s');
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write_be32(*f, 4);
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write_be32(*f, 0);
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f->put('r'); // 'r': register classes
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write_be32(*f, 4); // length in bytes
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write_be32(*f, 0); // no register classes
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f->put('h');
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f->put('s'); // 's': register initial values
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write_be32(*f, 4); // length in bytes
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write_be32(*f, 0); // no register initial values
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f->put('h'); // 'h': hierarchy information
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// TODO: get rid of std::string copy
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std::string h_buffer_str = h_buffer.str();
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write_be32(*f, h_buffer_str.size());
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f->write(h_buffer_str.data(), h_buffer_str.size());
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write_be32(*f, h_buffer_str.size()); // length in bytes
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f->write(h_buffer_str.data(), h_buffer_str.size()); // data
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#if 1
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f->put('a');
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write_be32(*f, 0); // size to be filled later
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f->put('a'); // 'a': additional AIG (used for holes)
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write_be32(*f, 0); // length in bytes (to be filled later)
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auto holes_aiger_start = f->tellp();
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{
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AigerWriter holes_writer;
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@ -1331,7 +1350,7 @@ struct XAigerWriter : AigerWriter {
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auto holes_aiger_size = f->tellp() - holes_aiger_start;
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f->seekp(holes_aiger_start, std::ios::beg);
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f->seekp(-4, std::ios::cur);
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write_be32(*f, holes_aiger_size);
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write_be32(*f, holes_aiger_size); // length in bytes
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#endif
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f->seekp(0, std::ios::end);
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