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785 Commits

Author SHA1 Message Date
Akash Levy d520cb42cc
Merge branch 'YosysHQ:main' into main 2025-05-22 10:30:58 -07:00
George Rennie 6331f92d00
Merge pull request #5101 from georgerennie/george/opt_expr_shift_ovfl 
opt_expr: fix shift optimization with overflowing shift amount
 2025-05-22 15:16:19 +01:00
Akash Levy 3c7c004c31 Fix stuff 2025-05-15 15:27:12 -07:00
Akash Levy 1f00bf0057 Bump yosys to latest 2025-05-15 14:44:26 -07:00
Emil J 3823157c25
Merge pull request #5080 from akashlevy/muldiv_c 
Add `muldiv_c` peepopt
 2025-05-15 11:03:25 +02:00
George Rennie 748600c167
small whitespace cleanup (#5119) 2025-05-14 15:18:57 +02:00
Akash Levy 1990c1fac5 Reduce pass verbosity 2025-05-13 20:42:47 -07:00
Akash Levy d6975c1d5f Fix src attr inheritance in opt_share 2025-05-13 20:05:16 -07:00
George Rennie 0dcd94b6ad opt_expr: saturate shift amount instead of overflowing for large shifts 2025-05-07 14:41:13 +02:00
Akash Levy 4bd91fbb11 Add `muldiv_c` peepopt pass 2025-04-30 08:06:59 -07:00
Akash Levy 5e0d59ca90
Merge branch 'YosysHQ:main' into main 2025-04-28 18:12:42 -07:00
George Rennie c952ab417f opt_expr: only sign extend shift arguments for arithmetic right shift 2025-04-26 12:40:04 +02:00
Akash Levy 9665a76876 Undo bad wreduce change 2025-04-22 03:40:34 -07:00
Akash Levy 5f5ed1b29e Merge upstream yosys 2025-04-21 17:36:24 -07:00
Jannis Harder 4b273a4ae9 share: Cleanup and additional testing 
Fixes a typo and adds another test case that triggers the fallback
behavior as the existing tests all trigger the new optimization.
 2025-04-15 12:34:46 +02:00
Jannis Harder 7593b5b224 share: Only print optimized activation patterns when different 
This removes redundant information from the log and makes it easier to
spot where the new optimization had an effect.
 2025-04-15 12:34:46 +02:00
Jannis Harder 27ed77ea24 share: Keep filtered activation patterns for the supercell 
The previous commit introduced code that optimizes the activation
patterns to be able to generate smaller activation logic. The resulting
supercell was then enqueued as shareable using those optimized
activation patterns. The condition represented by the optimized patterns
is an over-approximation of the actual activiation condition. This means
using it as activiation for the supercell loses precision and pessimises
sharing of the supercell with further cells, breaking the sat/share
test.

This commit fixes that by using the optimized activiation patterns only
for the generation of activation logic and using the original patterns
for enqueuing the supercell.
 2025-04-15 12:34:46 +02:00
Jannis Harder 6dff9e7787 share: Restrict activation patterns to potentially relevant signals 
In case the two sets of activation patterns are mutually exclusive
without considering the logic feeding into the activation signals, an
activation condition can only be relevant if present in both sets with
opposite polarity.

This detects pattern-only mutual exclusion by running an additional SAT
query before importing the input cone logic. If that is already UNSAT,
we remove all non-relevant condition and re-simplify the remaining
patterns.

In cases of pattern-only mutual exclusion, this will often produce much
smaller selection logic and avoid the more costly SAT query that
includes the input cones.
 2025-04-15 12:34:46 +02:00
Martin Povišer 38beae1e06
Merge pull request #4946 from povik/cost-cc-enhance 
cost: Add `$mem_v2`, `$macc_v2` estimates
 2025-04-14 11:08:59 +02:00
Akash Levy e241c9d513
Merge branch 'YosysHQ:main' into main 2025-04-10 14:28:10 -07:00
Krystine Sherwin cd3b914132
Reinstate #4768 
Revert the reversion so that we can fix the bugs that the PR missed.
 2025-04-08 11:58:05 +12:00
Akash Levy c0a6985adb
Merge branch 'YosysHQ:main' into main 2025-04-07 14:48:16 -07:00
Akash Levy de375d6542 Accommodate reversion and fix wreduce naming 2025-04-07 07:35:39 -07:00
Akash Levy 06c614a010
Merge branch 'YosysHQ:main' into main 2025-04-07 07:28:06 -07:00
Miodrag Milanović d49364d96f
Revert "Refactor full_selection" 2025-04-07 12:11:55 +02:00
Akash Levy 0dab4308a3 Actual merge here 2025-04-06 18:53:43 -07:00
KrystalDelusion 98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections 
Refactor full_selection
 2025-04-05 14:15:27 +13:00
Akash Levy 276800c39b wreduce shifter signedness fix 2025-04-04 14:27:38 -07:00
Krystine Sherwin 406b400458
opt_expr: Fix #4590 
If all the (non-select) inputs of a `$_MUX{4,8,16}_` are undefined, replace it, just like we do for `$mux` and `$_MUX_`.
Add `tests/opt/opt_expr_mux_undef.ys` to verify this.

This doesn't do any const folding on the wide muxes, or shrinking to less wide muxes.  It only handles the case where all inputs are 'x and the mux can be completely removed.
 2025-04-04 12:25:31 +13:00
Akash Levy 439d859bba
Merge branch 'YosysHQ:main' into main 2025-04-03 10:48:42 -07:00
Anhijkt 6b5507139e opt_expr: requsted changes 2025-04-01 20:37:22 +03:00
Akash Levy 3f00e57076 Improve the naming for opt_reduce 2025-03-31 01:22:42 -07:00
Anhijkt 83b095ab6c opt_expr: optimize pow of 2 cells 2025-03-30 15:43:41 +03:00
Akash Levy 3d13f7aae2 Bump to latest 2025-03-26 14:56:10 -07:00
KrystalDelusion a647731812
Merge pull request #4677 from YosysHQ/emil/opt_merge-hashing 
opt_merge: hashing performance and correctness
 2025-03-25 10:36:02 +13:00
Akash Levy 95f489beec Merge nice gzip refactor 2025-03-20 16:47:12 -07:00
KrystalDelusion b06a661913
Merge pull request #4834 from YosysHQ/emil/gzip-refactor 
Memory-efficient zlib usage across Liberty file consumers
 2025-03-21 10:01:00 +13:00
Akash Levy d1f0c38bac
Merge branch 'YosysHQ:main' into main 2025-03-19 19:32:42 -07:00
Emil J b33787edcb
Merge pull request #4948 from YosysHQ/emil/share-fix-log-again 
share: re-add SAT solver cell count to log message
 2025-03-19 13:54:17 +01:00
Emil J. Tywoniak 4f3fdc8457 io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
Emil J. Tywoniak 061cf5c6c4 share: re-add SAT solver cell count to log message 2025-03-19 10:27:23 +01:00
Martin Povišer 91cd382f8b macc: Rename 'ports' to 'terms' throughout codebase 2025-03-18 13:25:10 +01:00
Akash Levy d289e5ef1c
Merge branch 'YosysHQ:main' into main 2025-03-17 10:45:27 -07:00
Akash Levy a08ab5a67b Add opt_expr's missing mux_ornot and mux_andnot cases (still needs testing) 2025-03-17 04:09:28 -07:00
Akash Levy 4bf3338e1e Muxpack until not possible 2025-03-17 02:29:12 -07:00
Emil J 05cd1e2942
Merge pull request #4904 from YosysHQ/emil/share-limit-effort 
share: add -pattern-limit to limit analysis effort
 2025-03-15 18:00:42 +01:00
Krystine Sherwin a3968d43f0
Drop deprecation on Design::selected_modules() 
Instead, change the default `Design::selected_modules()` to match the behaviour (i.e. `selected_unboxed_modules_warn()`) because it's a lot of files to touch and they don't really _need_ to be updated.
Also change `Design::selected_whole_modules()` users over to `Design::selected_unboxed_whole_modules()`, except `attrmap` because I'm not convinced it should be ignoring boxes.  So instead, leave the deprecation warning for that one use and come back to the pass another time.
 2025-03-14 14:08:56 +13:00
Alain Dargelas 6b6c5c2c19 Actually re-enable pass 2025-03-13 14:48:14 -07:00
Alain Dargelas 68312d046a Fix Yosys test failures 2025-03-13 14:15:13 -07:00
Akash Levy 0a68eb32b3 Disable sub-neg peepopt 2025-03-13 01:55:14 -07:00