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17900 Commits

Author SHA1 Message Date
nella 2c12545cf3 opt_dff restructure. 2026-01-21 10:08:44 +01:00
Miodrag Milanović 2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy 
Avoid spurious copy in `IdStringCollector::trace_named()`
 2026-01-21 08:30:07 +01:00
Stan Lee d2e8f9b8a8 first round fixes 2026-01-20 21:45:13 -08:00
Robert O'Callahan 2c0448a81b Avoid spurious copy in `IdStringCollector::trace_named()` 2026-01-21 03:31:56 +00:00
github-actions[bot] 57ac113b7f Bump version 2026-01-21 00:27:51 +00:00
Stan Lee 29061d3051 leave no room for err 2026-01-20 15:55:05 -08:00
Stan Lee 45bd3f4515 change splitcells pass to remove some bracket from register names in blast mode 2026-01-20 15:50:43 -08:00
Stan Lee 60a81a2676 reg rename pass reads from vcd for original widths 2026-01-20 15:35:13 -08:00
Stan Lee a5106da733 line reduction 2026-01-20 11:56:57 -08:00
Stan Lee 0ea4bb8a2d comment 2026-01-20 11:55:54 -08:00
Stan Lee 80364c608e significantly cleaner 2026-01-20 11:29:56 -08:00
Miodrag Milanović bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017 
verific: add explicit System Verilog 2017 option
 2026-01-20 14:44:46 +01:00
Miodrag Milanovic d0fa4781c6 verific: Fix -sv2017 message and formatting 2026-01-20 08:07:26 +01:00
Gus Smith 491276983e Add test 2026-01-19 18:34:55 -08:00
Martin Povišer 90673cb0a2 techmap: Use `-icells` mode of frontend instead of type fixup 2026-01-19 16:49:49 -08:00
Martin Povišer f67d4bcfa4 verilog: Do not set `module_not_derived` on internal cells 2026-01-19 16:48:13 -08:00
github-actions[bot] 49e5950791 Bump version 2026-01-20 00:26:10 +00:00
Stan Lee c471014878 slightly cleaner 2026-01-19 12:58:36 -08:00
Stan Lee 6303eed1b4 works hierarchy 2026-01-19 12:22:22 -08:00
Stan Lee 186fc15f8f passes simple test 2026-01-19 12:10:48 -08:00
Stan Lee e678e2a0c3 every step except wire connecting 2026-01-19 11:20:11 -08:00
Stan Lee 15026033a3 annotate original register width 2026-01-19 11:19:41 -08:00
Krystine Sherwin 0f478a5952
tests/bug5574: Fix for non threaded abc 2026-01-20 05:56:14 +13:00
Miodrag Milanovic cc3038f468 verific: Fix -sv2017 message 2026-01-19 16:32:46 +01:00
Miodrag Milanović 2bde91b6ef
Merge pull request #5618 from YosysHQ/update_abc 
Update ABC as per 2026-01-19
 2026-01-19 15:45:02 +01:00
nella 67d10a41e8
Merge pull request #5617 from YosysHQ/emil/consteval-description 
consteval: describe
 2026-01-19 14:56:24 +01:00
Miodrag Milanovic 691983be14 Update ABC as per 2026-01-19 2026-01-19 12:08:24 +01:00
Emil J 7880f31acb
Merge pull request #5531 from YosysHQ/emil/shuffle-contributing-docs 
docs: shuffle and expand contributing info
 2026-01-19 12:02:49 +01:00
Emil J. Tywoniak c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Emil J. Tywoniak befadf6d4d consteval: describe 2026-01-19 12:00:18 +01:00
Miodrag Milanović 9355fa5037
Merge pull request #5616 from rocallahan/fix-unused-var-warning 
Fix warning about unused variable in `dffunmap`.
 2026-01-19 08:24:48 +01:00
Robert O'Callahan 28c199fbbd Fix warning about unused variable in `dffunmap`. 2026-01-19 03:25:09 +00:00
Akash Levy 7792f0644a
Merge branch 'YosysHQ:main' into main 2026-01-18 17:17:45 -08:00
KrystalDelusion 8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err 
Improve error handling in sim
 2026-01-19 09:51:12 +13:00
Stan Lee 4a1af73ec0 activity pass and a vcd writer bug fix 2026-01-16 16:32:04 -08:00
Miodrag Milanovic d095d2c405 verific: add explicit System Verilog 2017 option 2026-01-16 07:56:53 +01:00
Natalia ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Akash Levy 33ddae41c3 Remove lut2bmux from silimate after upstreaming 2026-01-14 20:24:26 -08:00
Akash Levy ef98c62bf2 Merge 2026-01-14 18:34:16 -08:00
Natalia d5e1647d11 fix tests with truncation issues 2026-01-14 18:03:30 -08:00
github-actions[bot] 967b47d984 Bump version 2026-01-15 00:24:54 +00:00
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width 
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
 2026-01-14 14:58:53 -08:00
Natalia 60ac3670cb Fix truncation issue in opt_balance_tree pass 
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.

For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)

Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
 2026-01-14 13:14:56 -08:00
Emil J. Tywoniak ddf3c6c8b7 blif: add -gatesi test 2026-01-14 21:41:56 +01:00
kamay e0077b188d Add gatesi_mode in BLIF format 2026-01-14 21:41:56 +01:00
nella 763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string 
Add rtlil string getters
 2026-01-14 19:00:47 +01:00
nella 210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00
github-actions[bot] 4c1a18f01d Bump version 2026-01-14 06:40:44 +00:00
Natalia Kokoromyti 6aef8ea8ab Add missing <deque> include for MSVC compatibility 2026-01-13 15:31:46 -08:00
nataliakokoromyti 8a596f330a Update lut2mux.cc 2026-01-13 15:02:17 -08:00