4 Commits

Include renames

Author	SHA1	Message	Date
abhinavputhran	314d01b35f	changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change	2026-03-08 20:14:03 -04:00
abhinavputhran	47c2257f82	setundef: more tests! and wire selection in -init mode	2026-03-08 19:41:31 -04:00
abhinavputhran	c23ba3f917	I think CI runs within the tests directory based on error so I changed the file path	2026-03-08 18:15:35 -04:00
abhinavputhran	5048dac854	setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer	2026-03-06 18:12:03 -05:00