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28 lines
680 B
Plaintext
28 lines
680 B
Plaintext
# Test that setundef -zero respects wire selection: only selected wire is changed
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read_verilog <<EOT
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module test;
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wire a = 1'bx;
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wire b = 1'bx;
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endmodule
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EOT
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setundef -zero w:a
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sat -prove a 0
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design -reset
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# Test that setundef -undriven -zero respects wire selection
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read_verilog <<EOT
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module test(output wire a, output wire b);
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assign a = 1'b0;
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endmodule
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EOT
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setundef -undriven -zero w:b
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sat -prove b 0
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design -reset
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# Test that setundef -init respects cell selection: only selected FF gets init set
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read_rtlil setundef_selection_ff.il
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setundef -init -zero c:myff_a
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# only wire a should have init attribute, not b
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select -assert-count 1 w:* a:init %i
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design -reset
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