yosys

Commit Graph

Author	SHA1	Message	Date
Miodrag Milanovic	48a3dcc02a	End of file fix	2026-06-23 07:23:41 +02:00
George Haworth	aba5b279c6	Fix RAMB36E1/E2 SDP parity port mapping typo DIPBDIP/DINPBDINP condition checked PORT_W_WIDTH == 71, which never matches any valid SDP width. Should be 72, matching the DIBDI/DINBDIN condition on the line above. This caused data bits 68-69 to be silently overwritten with copies of bits 64-65 on every write. Affects both xc6v (RAMB36E1, Artix-7/Kintex-7/Virtex-7) and xcu (RAMB36E2, UltraScale/UltraScale+) mapping templates. The RAMB18E1/E2 equivalents correctly use == 36.	2026-04-18 19:10:18 +03:00
Marcelina Kościelnicka	3b2f95953c	xilinx: Use `memory_libmap` pass.	2022-05-18 17:32:56 +02:00

Author

SHA1

Message

Date

Miodrag Milanovic

48a3dcc02a

End of file fix

2026-06-23 07:23:41 +02:00

George Haworth

aba5b279c6

Fix RAMB36E1/E2 SDP parity port mapping typo

DIPBDIP/DINPBDINP condition checked PORT_W_WIDTH == 71, which never
matches any valid SDP width. Should be 72, matching the DIBDI/DINBDIN
condition on the line above. This caused data bits 68-69 to be
silently overwritten with copies of bits 64-65 on every write.

Affects both xc6v (RAMB36E1, Artix-7/Kintex-7/Virtex-7) and xcu
(RAMB36E2, UltraScale/UltraScale+) mapping templates. The RAMB18E1/E2
equivalents correctly use == 36.

2026-04-18 19:10:18 +03:00

Marcelina Kościelnicka

3b2f95953c

xilinx: Use `memory_libmap` pass.

2022-05-18 17:32:56 +02:00

3 Commits