From f925de7dc4580994aba8ebd63288c6445a156ecb Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Wed, 26 Aug 2026 19:17:27 +0200
Subject: [PATCH] techlibs, ffinit: signorm fixes

---
 kernel/ffinit.h             | 10 ++++++----
 techlibs/common/mul2dsp.v   | 32 ++++++++++++++++++++++++++++++++
 techlibs/ice40/ice40_opt.cc |  9 ++++++---
 3 files changed, 44 insertions(+), 7 deletions(-)

diff --git a/kernel/ffinit.h b/kernel/ffinit.h
index 8b4758f60..4f00b9213 100644
--- a/kernel/ffinit.h
+++ b/kernel/ffinit.h
@@ -53,12 +53,14 @@ struct FfInitVals
 			if (val != State::S0 && val != State::S1 && bit.wire != nullptr)
 				continue;
 
-			if (initbits.count(bit)) {
-				if (initbits.at(bit).first != val)
+			auto found = initbits.find(bit);
+			if (found != initbits.end()) {
+				if (found->second.first == val || val == State::Sx)
+					continue;
+				if (found->second.first != State::Sx)
 					log_error("Conflicting init values for signal %s (%s = %s != %s).\n",
 							log_signal(bit), log_signal(SigBit(wire, i)),
-							log_signal(val), log_signal(initbits.at(bit).first));
-				continue;
+							log_signal(val), log_signal(found->second.first));
 			}
 
 			initbits[bit] = std::make_pair(val,SigBit(wire,i));
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index be0172dc9..de335eb82 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -49,6 +49,38 @@ $fatal(1, "Macro DSP_NAME must be defined");
 `define MAX(a,b) (a > b ? a : b)
 `define MIN(a,b) (a < b ? a : b)
 
+(* blackbox *)
+module \$__mul (A, B, Y);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	(* force_downto *)
+	input [A_WIDTH-1:0] A;
+	(* force_downto *)
+	input [B_WIDTH-1:0] B;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] Y;
+endmodule
+
+(* blackbox *)
+module \$__soft_mul (A, B, Y);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	(* force_downto *)
+	input [A_WIDTH-1:0] A;
+	(* force_downto *)
+	input [B_WIDTH-1:0] B;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] Y;
+endmodule
+
 (* techmap_celltype = "$mul $__mul" *)
 module _80_mul (A, B, Y);
 	parameter A_SIGNED = 0;
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 67d3813a7..ab68a785d 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -138,16 +138,19 @@ static void run_ice40_opts(Module *module)
 				module->design->scratchpad_set_bool("opt.did_something", true);
 				log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						module, cell, log_signal(replacement_output));
-				cell->type = ID($lut);
 				auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
-				cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
-				cell->setPort(ID::Y, cell->getPort(ID::O));
+				RTLIL::SigSpec sig_a { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) };
+				RTLIL::SigSpec sig_y = cell->getPort(ID::O);
+				cell->unsetPort(ID::A);
 				cell->unsetPort(ID::B);
 				cell->unsetPort(ID::CI);
 				cell->unsetPort(ID(I0));
 				cell->unsetPort(ID(I3));
 				cell->unsetPort(ID::CO);
 				cell->unsetPort(ID::O);
+				cell->type = ID($lut);
+				cell->setPort(ID::A, std::move(sig_a));
+				cell->setPort(ID::Y, std::move(sig_y));
 				cell->setParam(ID::WIDTH, 4);
 				cell->unsetParam(ID(I3_IS_CI));
 			}