From e091c1653991617a9be43b2abb5e373e2418c9c9 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 14 Sep 2026 10:16:34 +0200
Subject: [PATCH 1/2] Use <inlined> for heredoc input filename

---
 kernel/register.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/kernel/register.cc b/kernel/register.cc
index 14484c25a..a0746b4a7 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -485,8 +485,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
 			if (filename.size() <= 2)
 				log_error("Missing EOT marker in here document!\n");
 			std::string eot_marker = filename.substr(2);
-			if (Frontend::current_script_file == nullptr)
-				filename = "<stdin>";
+			filename = (Frontend::current_script_file == nullptr) ?  "<stdin>" : "<inlined>";
 			last_here_document.clear();
 			while (1) {
 				std::string buffer;

From 5cdba4fbd797427455e23017594593cc5084ff31 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 14 Sep 2026 10:35:11 +0200
Subject: [PATCH 2/2] Update tests to reflect change to <inlined>

---
 tests/arch/ice40/ice40_wrapcarry.ys   |  4 ++--
 tests/various/mem2reg.ys              |  4 ++--
 tests/various/primitives.ys           | 12 ++++++------
 tests/various/printattr.ys            |  2 +-
 tests/various/rename_scramble_name.ys |  2 +-
 tests/various/rename_unescape.ys      |  4 ++--
 tests/various/src.ys                  |  4 ++--
 tests/verilog/constparser_f.ys        |  2 +-
 tests/verilog/constparser_g.ys        |  2 +-
 9 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/tests/arch/ice40/ice40_wrapcarry.ys b/tests/arch/ice40/ice40_wrapcarry.ys
index 74319c480..f84338439 100644
--- a/tests/arch/ice40/ice40_wrapcarry.ys
+++ b/tests/arch/ice40/ice40_wrapcarry.ys
@@ -50,5 +50,5 @@ select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
 select -assert-count 1 a:keep=1 a:SB_CARRY.\foo=bar %i a:SB_CARRY.\answer=42 %i a:SB_LUT4.\blah=blah %i a:SB_LUT4.\answer=43 %i
 
 ice40_wrapcarry -unwrap
-select -assert-count 1 c:carry a:src=<<EOT:3.11-8.3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i
-select -assert-count 1 c:adder a:src=<<EOT:12.4-18.3 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i
+select -assert-count 1 c:carry a:src=<inlined>:3.11-8.3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i
+select -assert-count 1 c:adder a:src=<inlined>:12.4-18.3 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i
diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys
index ba94787bc..aeaa9a5a6 100644
--- a/tests/various/mem2reg.ys
+++ b/tests/various/mem2reg.ys
@@ -9,6 +9,6 @@ EOT
 
 proc
 cd top
-select -assert-count 1 m:data1 a:src=<<EOT:4.43-4.48 %i
-select -assert-count 2 w:data2[*] a:src=<<EOT:5.41-5.46 %i
+select -assert-count 1 m:data1 a:src=<inlined>:4.43-4.48 %i
+select -assert-count 2 w:data2[*] a:src=<inlined>:5.41-5.46 %i
 select -assert-none a:mem2reg
diff --git a/tests/various/primitives.ys b/tests/various/primitives.ys
index 9307ca50f..eeab96770 100644
--- a/tests/various/primitives.ys
+++ b/tests/various/primitives.ys
@@ -8,9 +8,9 @@ xor (y[4], a, b);
 xnor (y[5], a, b);
 endmodule
 EOT
-select -assert-count 1 t:$and a:src=<<EOT:2.4-2.17 %i
-select -assert-count 1 t:$and a:src=<<EOT:3.5-3.18 %i
-select -assert-count 1 t:$or a:src=<<EOT:4.3-4.16 %i
-select -assert-count 1 t:$or a:src=<<EOT:5.4-5.17 %i
-select -assert-count 1 t:$xor a:src=<<EOT:6.4-6.17 %i
-select -assert-count 1 t:$xor a:src=<<EOT:7.5-7.18 %i
+select -assert-count 1 t:$and a:src=<inlined>:2.4-2.17 %i
+select -assert-count 1 t:$and a:src=<inlined>:3.5-3.18 %i
+select -assert-count 1 t:$or a:src=<inlined>:4.3-4.16 %i
+select -assert-count 1 t:$or a:src=<inlined>:5.4-5.17 %i
+select -assert-count 1 t:$xor a:src=<inlined>:6.4-6.17 %i
+select -assert-count 1 t:$xor a:src=<inlined>:7.5-7.18 %i
diff --git a/tests/various/printattr.ys b/tests/various/printattr.ys
index afc6d8eb6..2228d12c8 100644
--- a/tests/various/printattr.ys
+++ b/tests/various/printattr.ys
@@ -1,5 +1,5 @@
 logger -expect log ".*cells_not_processed=[01]* .*" 1
-logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
+logger -expect log ".*src=.<inlined>:1\.1-9\.10. .*" 1
 read_verilog <<EOT
 module mux2(a, b, s, y);
 	input a, b, s;
diff --git a/tests/various/rename_scramble_name.ys b/tests/various/rename_scramble_name.ys
index 9a36d0922..ca0a15921 100644
--- a/tests/various/rename_scramble_name.ys
+++ b/tests/various/rename_scramble_name.ys
@@ -28,4 +28,4 @@ hierarchy -top top
 rename -seed 2 -scramble-name c:bar
 select -assert-none c:bar
 select -assert-count 1 c:$_*_
-select -assert-none c:$_*_ w:* foo/c:$add$<<EOF:2$1 %% %n
+select -assert-none c:$_*_ w:* foo/c:$add$<inlined>:2$1 %% %n
diff --git a/tests/various/rename_unescape.ys b/tests/various/rename_unescape.ys
index 2bb5286cc..ee8dfa712 100644
--- a/tests/various/rename_unescape.ys
+++ b/tests/various/rename_unescape.ys
@@ -27,7 +27,7 @@ select -assert-count 1 w:$e
 # Colliding with keyword
 select -assert-count 1 w:wire
 # Don't touch internal names
-select -assert-count 1 w:$add$<<EOF:*$1_Y
+select -assert-count 1 w:$add$<inlined>:*$1_Y
 
 rename -unescape
 
@@ -38,7 +38,7 @@ select -assert-count 1 w:d_
 select -assert-count 1 w:d__1
 select -assert-count 1 w:_e
 select -assert-count 1 w:wire_
-select -assert-count 1 w:$add$<<EOF:*$1_Y
+select -assert-count 1 w:$add$<inlined>:*$1_Y
 
 # Ports are updated during rename
 design -reset
diff --git a/tests/various/src.ys b/tests/various/src.ys
index 89d6700ca..3913c61fb 100644
--- a/tests/various/src.ys
+++ b/tests/various/src.ys
@@ -1,5 +1,5 @@
-logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1
-logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1
+logger -expect warning "wire '\\o' is assigned in a block at <inlined>:2.11-2.17" 1
+logger -expect warning "wire '\\p' is assigned in a block at <inlined>:3.11-3.16" 1
 read_verilog <<EOT
 module top(input i, output o, p);
 always @* o <= i;
diff --git a/tests/verilog/constparser_f.ys b/tests/verilog/constparser_f.ys
index 4c5eff46f..a251ac3d7 100644
--- a/tests/verilog/constparser_f.ys
+++ b/tests/verilog/constparser_f.ys
@@ -1,4 +1,4 @@
-logger -expect prefix-error "<<EOT:2: ERROR: Digit larger than 1 used in in base-2 constant." 1
+logger -expect prefix-error "<inlined>:2: ERROR: Digit larger than 1 used in in base-2 constant." 1
 read_verilog <<EOT
 module test (y);
     output signed [2:0] y = 1'bf;
diff --git a/tests/verilog/constparser_g.ys b/tests/verilog/constparser_g.ys
index 37e31ba20..b75116ac2 100644
--- a/tests/verilog/constparser_g.ys
+++ b/tests/verilog/constparser_g.ys
@@ -1,4 +1,4 @@
-logger -expect prefix-error "<<EOT:2: ERROR: syntax error, unexpected invalid token, expecting TOK_BASED_CONSTVAL" 1
+logger -expect prefix-error "<inlined>:2: ERROR: syntax error, unexpected invalid token, expecting TOK_BASED_CONSTVAL" 1
 read_verilog <<EOT
 module test (y);
     output signed [2:0] y = 1'bg;