From ee75cd3ea0261ecc058944cf691c2b112118a5b9 Mon Sep 17 00:00:00 2001 From: Lofty Date: Mon, 10 Aug 2026 13:52:36 +0100 Subject: [PATCH] synth_lattice: remove classic ABC mapping --- techlibs/lattice/synth_lattice.cc | 79 ++++++++----------------------- tests/arch/machxo2/lutram.ys | 2 +- tests/arch/machxo2/mux.ys | 6 +-- tests/arch/nexus/add_sub.ys | 10 ---- tests/arch/nexus/counter.ys | 3 +- tests/arch/nexus/logic.ys | 2 +- 6 files changed, 27 insertions(+), 75 deletions(-) diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index a6daf8f85..4fb40ad17 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -104,10 +104,7 @@ struct SynthLatticePass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -dff\n"); - log(" run 'abc'/'abc9' with -dff option\n"); - log("\n"); - log(" -retime\n"); - log(" run 'abc' with '-dff -D 1' options\n"); + log(" run 'abc9' with -dff option\n"); log("\n"); log(" -noccu2\n"); log(" do not use CCU2 cells in output netlist\n"); @@ -131,12 +128,6 @@ struct SynthLatticePass : public ScriptPass log(" -asyncprld\n"); log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n"); log("\n"); - log(" -abc2\n"); - log(" run two passes of 'abc' for slightly improved logic density\n"); - log("\n"); - log(" -noabc9\n"); - log(" disable use of new ABC9 flow\n"); - log("\n"); log(" -iopad\n"); log(" insert IO buffers\n"); log(" (by default enabled on Nexus FPGAs)\n"); @@ -170,9 +161,9 @@ struct SynthLatticePass : public ScriptPass } string top_opt, edif_file, json_file, family, latches; - bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp; + bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, iopad, nodsp, no_rw_check, have_dsp; bool cmp2softlogic; - string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default, widelut_abc; + string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default; bool is_nexus; std::vector dsp_rules; @@ -190,9 +181,6 @@ struct SynthLatticePass : public ScriptPass asyncprld = false; flatten = true; dff = false; - retime = false; - abc2 = false; - abc9 = true; iopad = false; nodsp = false; no_rw_check = false; @@ -206,13 +194,11 @@ struct SynthLatticePass : public ScriptPass is_nexus = false; map_ram_default = ""; cells_map = ""; - widelut_abc = "4:7"; } void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; - bool force_abc9 = false; bool force_widelut = false; bool force_iopad = false; clear_flags(); @@ -257,7 +243,7 @@ struct SynthLatticePass : public ScriptPass continue; } if (args[argidx] == "-retime") { - retime = true; + // Removed: ABC9 does not support retiming. continue; } if (args[argidx] == "-noccu2") { @@ -291,17 +277,15 @@ struct SynthLatticePass : public ScriptPass continue; } if (args[argidx] == "-abc2") { - abc2 = true; + // Removed continue; } if (args[argidx] == "-abc9") { - // removed, ABC9 is on by default. - force_abc9 = true; + // Removed: ABC9 is on by default. continue; } if (args[argidx] == "-noabc9") { - force_abc9 = true; - abc9 = false; + // Removed: ABC9 is on by default. continue; } if (args[argidx] == "-iopad") { @@ -358,7 +342,6 @@ struct SynthLatticePass : public ScriptPass cells_map = "_trellis"; have_dsp = false; if (!force_widelut) nowidelut = true; - if (!force_abc9) abc9 = false; } else if (family == "lifcl" || family == "lfd2nx") { is_nexus = true; @@ -370,9 +353,7 @@ struct SynthLatticePass : public ScriptPass have_dsp = true; map_ram_default = " -no-auto-huge"; cells_map = "_nexus"; - widelut_abc = "4:5"; if (!force_iopad) iopad = true; - if (!force_abc9) abc9 = false; /* } else if (family == "xo" || family == "pm") { } else if (family == "xp" || @@ -389,9 +370,6 @@ struct SynthLatticePass : public ScriptPass if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (abc9 && retime) - log_cmd_error("-retime option not currently compatible with -abc9!\n"); - log_header(design, "Executing SYNTH_LATTICE pass.\n"); log_push(); @@ -500,8 +478,6 @@ struct SynthLatticePass : public ScriptPass run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]"); } run("opt -fast"); - if (retime || help_mode) - run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_ffs")) @@ -532,8 +508,8 @@ struct SynthLatticePass : public ScriptPass run("dfflegalize" + dfflegalize_args, "($_*DFFE_* only if not -nodffe)"); } run("opt_merge"); - if ((abc9 && dff) || help_mode) - run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)"); + if (dff || help_mode) + run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -dff)"); run("techmap -D NO_LUT -map +/lattice/cells_map" + cells_map + ".v"); run("opt_expr -undriven -mux_undef"); run("simplemap"); @@ -544,38 +520,23 @@ struct SynthLatticePass : public ScriptPass if (check_label("map_luts")) { - if (abc2 || help_mode) - run("abc", " (only if -abc2)"); if (!asyncprld || help_mode) { if (latches == "error" || help_mode) run("check -latchonly -assert", "(skip if -asyncprld; only if -latches error, the default)"); run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)"); } - if (abc9) { - std::string abc9_opts; - if (nowidelut) - abc9_opts += " -maxlut 4"; - std::string k = "synth_lattice.abc9.W"; - if (active_design && active_design->scratchpad.count(k)) - abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); - else - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); - if (nowidelut) - abc9_opts += " -maxlut 4"; - if (dff) - abc9_opts += " -dff"; - run("abc9" + abc9_opts); - } else { - std::string abc_args = " -dress"; - if (nowidelut) - abc_args += " -lut 4"; - else - abc_args += " -lut " + widelut_abc; - if (dff) - abc_args += " -dff"; - run("abc" + abc_args); - } + std::string abc9_opts; + std::string k = "synth_lattice.abc9.W"; + if (active_design && active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); + else + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); + if (nowidelut) + abc9_opts += " -maxlut 4"; + if (dff) + abc9_opts += " -dff"; + run("abc9" + abc9_opts); run("clean"); } diff --git a/tests/arch/machxo2/lutram.ys b/tests/arch/machxo2/lutram.ys index 65af7b2c2..34c95909c 100644 --- a/tests/arch/machxo2/lutram.ys +++ b/tests/arch/machxo2/lutram.ys @@ -11,7 +11,7 @@ sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w1r -select -assert-count 20 t:LUT4 +select -assert-count 28 t:LUT4 select -assert-count 8 t:TRELLIS_DPR16X4 select -assert-count 8 t:TRELLIS_FF select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys index 6d4e10dc7..c2e636008 100644 --- a/tests/arch/machxo2/mux.ys +++ b/tests/arch/machxo2/mux.ys @@ -15,7 +15,7 @@ proc equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 2 t:LUT4 +select -assert-count 3 t:LUT4 select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D @@ -25,7 +25,7 @@ proc equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 5 t:LUT4 +select -assert-count 6 t:LUT4 select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D @@ -35,6 +35,6 @@ proc equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-max 12 t:LUT4 +select -assert-max 13 t:LUT4 select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/tests/arch/nexus/add_sub.ys b/tests/arch/nexus/add_sub.ys index 4317bab81..0f0aaa6a6 100644 --- a/tests/arch/nexus/add_sub.ys +++ b/tests/arch/nexus/add_sub.ys @@ -1,21 +1,11 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -design -save orig equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module stat -select -assert-count 10 t:LUT4 -select -assert-none t:IB t:OB t:VLO t:LUT4 %% t:* %D - -design -load orig - -equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -stat select -assert-count 6 t:LUT4 select -assert-count 4 t:WIDEFN9 select -assert-none t:IB t:OB t:VLO t:LUT4 t:WIDEFN9 %% t:* %D diff --git a/tests/arch/nexus/counter.ys b/tests/arch/nexus/counter.ys index 44421e377..bd041ea25 100644 --- a/tests/arch/nexus/counter.ys +++ b/tests/arch/nexus/counter.ys @@ -6,6 +6,7 @@ equiv_opt -assert -multiclock -map +/nexus/cells_sim.v synth_nexus # equivalency design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module stat +select -assert-count 1 t:INV select -assert-count 5 t:CCU2 select -assert-count 8 t:FD1P3DX -select -assert-none t:CCU2 t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D +select -assert-none t:INV t:CCU2 t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D diff --git a/tests/arch/nexus/logic.ys b/tests/arch/nexus/logic.ys index cff61b509..89205e4ca 100644 --- a/tests/arch/nexus/logic.ys +++ b/tests/arch/nexus/logic.ys @@ -4,5 +4,5 @@ proc equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 8 t:LUT4 +select -assert-count 5 t:LUT4 select -assert-none t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D