mirror of https://github.com/YosysHQ/yosys.git
Smallfixes
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parent
b1f4d0d8aa
commit
e25492e87a
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@ -393,8 +393,8 @@ log -push
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read_verilog <<EOT
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module top(
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input signed [3:0] a,
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output signed [7:0] y
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output signed [7:0] z,
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output signed [7:0] y,
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output signed [7:0] z
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);
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wire signed [7:0] add;
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assign add = a + 4'sd6;
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@ -414,8 +414,8 @@ log -push
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read_verilog <<EOT
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module top(
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input signed [3:0] a,
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output signed [7:0] y
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output signed [7:0] z,
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output signed [7:0] y,
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output signed [7:0] z
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);
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wire signed [7:0] add;
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assign add = a + 4'sd6;
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@ -435,8 +435,8 @@ log -push
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read_verilog <<EOT
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module top(
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input signed [3:0] a,
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output signed [7:0] y
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output signed [7:0] z,
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output signed [7:0] y,
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output signed [7:0] z
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);
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wire signed [7:0] sub;
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assign sub = a - 4'sd6;
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@ -456,8 +456,8 @@ log -push
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read_verilog <<EOT
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module top(
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input signed [3:0] a,
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output signed [7:0] y
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output signed [7:0] z,
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output signed [7:0] y,
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output signed [7:0] z
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);
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wire signed [7:0] sub;
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assign sub = a - 4'sd6;
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