From e25492e87aabe61421d4273d699a9bd4dd5475fd Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Thu, 11 Sep 2025 04:50:58 -0700
Subject: [PATCH] Smallfixes

---
 tests/peepopt/addsub_c.ys | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/tests/peepopt/addsub_c.ys b/tests/peepopt/addsub_c.ys
index d8e09cc1e..6a3888542 100644
--- a/tests/peepopt/addsub_c.ys
+++ b/tests/peepopt/addsub_c.ys
@@ -393,8 +393,8 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y
-	output signed [7:0] z,
+	output signed [7:0] y,
+	output signed [7:0] z
 );
 	wire signed [7:0] add;
 	assign add = a + 4'sd6;
@@ -414,8 +414,8 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y
-	output signed [7:0] z,
+	output signed [7:0] y,
+	output signed [7:0] z
 );
 	wire signed [7:0] add;
 	assign add = a + 4'sd6;
@@ -435,8 +435,8 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y
-	output signed [7:0] z,
+	output signed [7:0] y,
+	output signed [7:0] z
 );
 	wire signed [7:0] sub;
 	assign sub = a - 4'sd6;
@@ -456,8 +456,8 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y
-	output signed [7:0] z,
+	output signed [7:0] y,
+	output signed [7:0] z
 );
 	wire signed [7:0] sub;
 	assign sub = a - 4'sd6;