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Small adjustments

This commit is contained in:
Akash Levy 2025-09-11 04:47:28 -07:00
parent 8f5b20c423
commit b1f4d0d8aa
2 changed files with 17 additions and 17 deletions
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4
passes/opt/peepopt_addsub_c.pmg
View File

@ -1,7 +1,7 @@
pattern addsub_c
//
// Authored by Akash Levy of Silimate, Inc. under ISC license.
// Transforms add->add/sub_c into add_c canceling the constants out:
// Transforms add->add/sub_c into add_c folding the constants:
// y = (a +- b_const) +- c_const ===> a +- eval(b_const +- c_const)
//
@ -76,7 +76,7 @@ code
if (GetSize(c_const) > 32)
reject;
// Reuse/create new cell to drive the rewritten equation
// Reuse/create new cell to drive the folded expression
if (nusers(addsub1_y) != 2) {
cell = module->addCell(NEW_ID2_SUFFIX("asconst"), addsub1->type);
cell->attributes = addsub1->attributes;

30
tests/peepopt/addsub_c.ys
View File

@ -178,7 +178,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] add;
assign add = 4'sd6 + a;
@ -197,7 +197,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] sub;
assign sub = 4'sd6 - a;
@ -216,7 +216,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] sub;
assign sub = 4'sd6 - a;
@ -237,7 +237,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] add;
assign add = a + 4'sd6;
@ -256,7 +256,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] add;
assign add = a + 4'sd6;
@ -275,7 +275,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] sub;
assign sub = a - 4'sd6;
@ -294,7 +294,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] sub;
assign sub = a - 4'sd6;
@ -315,7 +315,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] add;
assign add = a + (-4'sd6);
@ -334,7 +334,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] add;
assign add = a + (-4'sd6);
@ -353,7 +353,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] sub;
assign sub = a - (-4'sd6);
@ -372,7 +372,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] sub;
assign sub = a - (-4'sd6);
@ -393,7 +393,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
output signed [7:0] z,
);
wire signed [7:0] add;
@ -414,7 +414,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
output signed [7:0] z,
);
wire signed [7:0] add;
@ -435,7 +435,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
output signed [7:0] z,
);
wire signed [7:0] sub;
@ -456,7 +456,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
output signed [7:0] z,
);
wire signed [7:0] sub;