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Support barriers in more backends.

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This commit is contained in:
nella
2026-09-30 14:51:44 +02:00
parent 9724afae7f
commit e15e8fb02c
4 changed files with 38 additions and 5 deletions
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backends/cxxrtl/cxxrtl_backend.cc
+4 -1
View File
@@ -200,7 +200,7 @@ bool is_extending_cell(RTLIL::IdString type)
bool is_inlinable_cell(RTLIL::IdString type)
{
return is_unary_cell(type) || is_binary_cell(type) || type.in(
ID($mux), ID($concat), ID($slice), ID($pmux), ID($bmux), ID($demux), ID($bwmux));
ID($mux), ID($concat), ID($slice), ID($pmux), ID($bmux), ID($demux), ID($bwmux), ID($barrier));
}
bool is_ff_cell(RTLIL::IdString type)
@@ -1214,6 +1214,9 @@ struct CxxrtlWorker {
f << ",";
f << cell->getParam(ID::OFFSET).as_int();
f << ">().val()";
// Barriers
} else if (cell->type == ID($barrier)) {
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
} else {
log_assert(false);
}
backends/firrtl/firrtl.cc
+2 -1
View File
@@ -975,7 +975,8 @@ struct FirrtlWorker
if (a_width < y_width) {
a_expr = stringf("pad(%s, %d)", a_expr, y_width);
}
wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width));
// $buf and $barrier have no Y_WIDTH
wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, GetSize(cell->getPort(ID::Y))));
cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, a_expr));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
backends/smv/smv.cc
+3 -3
View File
@@ -308,16 +308,16 @@ struct SmvWorker
continue;
}
if (cell->type.in(ID($not), ID($pos), ID($neg)))
if (cell->type.in(ID($not), ID($pos), ID($neg), ID($barrier)))
{
int width = GetSize(cell->getPort(ID::Y));
string expr_a, op;
if (cell->type == ID($not)) op = "!";
if (cell->type == ID($pos)) op = "";
if (cell->type.in(ID($pos), ID($barrier))) op = "";
if (cell->type == ID($neg)) op = "-";
if (cell->getParam(ID::A_SIGNED).as_bool())
if (cell->hasParam(ID::A_SIGNED) && cell->getParam(ID::A_SIGNED).as_bool())
{
definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)),
op.c_str(), rvalue_s(cell->getPort(ID::A), width)));
tests/various/barrier_backends.ys
+29
View File
@@ -0,0 +1,29 @@
# export of $barrier cells by backends (as a buffer), or as a cut for ABC
! mkdir -p temp
read_verilog -icells <<EOT
module top(input [3:0] a, b, output [3:0] y);
wire [3:0] t;
\$barrier #(.WIDTH(4)) bar (.A(a & b), .Y(t));
assign y = t & a;
endmodule
EOT
hierarchy -top top
select -assert-count 1 t:$barrier
write_functional_smt2 temp/barrier_f.smt2
write_functional_cxx temp/barrier_f.cc
write_smt2 temp/barrier.smt2
! grep -qF ' state)) ; \t' temp/barrier.smt2
write_firrtl temp/barrier.fir
! grep -qF 'wire bar: UInt<4>' temp/barrier.fir
write_smv temp/barrier.smv
! grep -qF '_t := resize(_$and$' temp/barrier.smv
write_cxxrtl temp/barrier.cc
! grep -qF '\bar ' temp/barrier.cc
write_btor temp/barrier.btor
write_aiger2 temp/barrier.aig