diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index ac69bda27..c13a4e5a0 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -200,7 +200,7 @@ bool is_extending_cell(RTLIL::IdString type)
 bool is_inlinable_cell(RTLIL::IdString type)
 {
 	return is_unary_cell(type) || is_binary_cell(type) || type.in(
-		ID($mux), ID($concat), ID($slice), ID($pmux), ID($bmux), ID($demux), ID($bwmux));
+		ID($mux), ID($concat), ID($slice), ID($pmux), ID($bmux), ID($demux), ID($bwmux), ID($barrier));
 }
 
 bool is_ff_cell(RTLIL::IdString type)
@@ -1214,6 +1214,9 @@ struct CxxrtlWorker {
 			f << ",";
 			f << cell->getParam(ID::OFFSET).as_int();
 			f << ">().val()";
+		// Barriers
+		} else if (cell->type == ID($barrier)) {
+			dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
 		} else {
 			log_assert(false);
 		}
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 87c5a00cc..244cc06cf 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -975,7 +975,8 @@ struct FirrtlWorker
 				if (a_width < y_width) {
 					a_expr = stringf("pad(%s, %d)", a_expr, y_width);
 				}
-				wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width));
+				// $buf and $barrier have no Y_WIDTH
+				wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, GetSize(cell->getPort(ID::Y))));
 				cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, a_expr));
 				register_reverse_wire_map(y_id, cell->getPort(ID::Y));
 				continue;
diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index 01f95ef45..7018aa014 100644
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -308,16 +308,16 @@ struct SmvWorker
 				continue;
 			}
 
-			if (cell->type.in(ID($not), ID($pos), ID($neg)))
+			if (cell->type.in(ID($not), ID($pos), ID($neg), ID($barrier)))
 			{
 				int width = GetSize(cell->getPort(ID::Y));
 				string expr_a, op;
 
 				if (cell->type == ID($not))  op = "!";
-				if (cell->type == ID($pos))  op = "";
+				if (cell->type.in(ID($pos), ID($barrier)))  op = "";
 				if (cell->type == ID($neg))  op = "-";
 
-				if (cell->getParam(ID::A_SIGNED).as_bool())
+				if (cell->hasParam(ID::A_SIGNED) && cell->getParam(ID::A_SIGNED).as_bool())
 				{
 					definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)),
 							op.c_str(), rvalue_s(cell->getPort(ID::A), width)));
diff --git a/tests/various/barrier_backends.ys b/tests/various/barrier_backends.ys
new file mode 100644
index 000000000..08dca072f
--- /dev/null
+++ b/tests/various/barrier_backends.ys
@@ -0,0 +1,29 @@
+# export of $barrier cells by backends (as a buffer), or as a cut for ABC
+! mkdir -p temp
+read_verilog -icells <<EOT
+module top(input [3:0] a, b, output [3:0] y);
+	wire [3:0] t;
+	\$barrier #(.WIDTH(4)) bar (.A(a & b), .Y(t));
+	assign y = t & a;
+endmodule
+EOT
+hierarchy -top top
+select -assert-count 1 t:$barrier
+
+write_functional_smt2 temp/barrier_f.smt2
+write_functional_cxx temp/barrier_f.cc
+
+write_smt2 temp/barrier.smt2
+! grep -qF ' state)) ; \t' temp/barrier.smt2
+
+write_firrtl temp/barrier.fir
+! grep -qF 'wire bar: UInt<4>' temp/barrier.fir
+
+write_smv temp/barrier.smv
+! grep -qF '_t := resize(_$and$' temp/barrier.smv
+
+write_cxxrtl temp/barrier.cc
+! grep -qF '\bar ' temp/barrier.cc
+
+write_btor temp/barrier.btor
+write_aiger2 temp/barrier.aig