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https://github.com/YosysHQ/yosys.git
synced 2026-10-06 01:53:53 +02:00
muxcover: avoid hang on loop through mux tree
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@@ -135,10 +135,15 @@ struct MuxcoverWorker
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pool<SigBit> wavefront;
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wavefront.insert(rootsig);
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bool has_loop = false;
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while (!wavefront.empty()) {
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SigBit bit = wavefront.pop();
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if (sig_to_mux.count(bit) && (bit == rootsig || !roots.count(bit))) {
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if (tree.muxes.count(bit)) {
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has_loop = true;
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break;
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}
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Cell *c = sig_to_mux.at(bit);
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tree.muxes[bit] = c;
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wavefront.insert(sigmap(c->getPort(ID::A)));
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@@ -146,6 +151,11 @@ struct MuxcoverWorker
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}
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}
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if (has_loop) {
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log(" Skipping tree at root %s: contains a logic loop.\n", log_signal(tree.root));
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continue;
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}
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if (!tree.muxes.empty()) {
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log(" Found tree with %d MUXes at root %s.\n", GetSize(tree.muxes), log_signal(tree.root));
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tree_list.push_back(tree);
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@@ -0,0 +1,35 @@
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read_verilog <<EOT
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module top(input s, d, output a);
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assign a = s ? a : d;
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endmodule
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EOT
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simplemap
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muxcover -mux4 -mux8
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select -assert-count 1 t:$_MUX_
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design -reset
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read_verilog <<EOT
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module top(input [3:0] s, input [3:0] d, output a);
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wire b = s[1] ? a : d[1];
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wire c = s[2] ? d[2] : d[3];
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wire e = s[3] ? b : c;
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assign a = s[0] ? e : d[0];
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endmodule
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EOT
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simplemap
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muxcover -mux4 -mux8
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select -assert-count 4 t:$_MUX_
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select -assert-none t:$_MUX4_ t:$_MUX8_
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design -reset
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read_verilog <<EOT
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module top(input s, a, b, c, output y);
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wire m = y ? b : a;
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assign y = s ? c : m;
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endmodule
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EOT
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simplemap
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muxcover -mux4=1 -dmux=0
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select -assert-count 1 t:$_MUX4_
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select -assert-count 1 t:$_MUX4_ %co:+[Y] t:$_MUX4_ %ci:+[S] %i w:* %i
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select -assert-none t:$_MUX_
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