diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index 719a346d8..8d26d376c 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -135,10 +135,15 @@ struct MuxcoverWorker
 
 			pool<SigBit> wavefront;
 			wavefront.insert(rootsig);
+			bool has_loop = false;
 
 			while (!wavefront.empty()) {
 				SigBit bit = wavefront.pop();
 				if (sig_to_mux.count(bit) && (bit == rootsig || !roots.count(bit))) {
+					if (tree.muxes.count(bit)) {
+						has_loop = true;
+						break;
+					}
 					Cell *c = sig_to_mux.at(bit);
 					tree.muxes[bit] = c;
 					wavefront.insert(sigmap(c->getPort(ID::A)));
@@ -146,6 +151,11 @@ struct MuxcoverWorker
 				}
 			}
 
+			if (has_loop) {
+				log("    Skipping tree at root %s: contains a logic loop.\n", log_signal(tree.root));
+				continue;
+			}
+
 			if (!tree.muxes.empty()) {
 				log("    Found tree with %d MUXes at root %s.\n", GetSize(tree.muxes), log_signal(tree.root));
 				tree_list.push_back(tree);
diff --git a/tests/various/muxcover_loop.ys b/tests/various/muxcover_loop.ys
new file mode 100644
index 000000000..41462e930
--- /dev/null
+++ b/tests/various/muxcover_loop.ys
@@ -0,0 +1,35 @@
+read_verilog <<EOT
+module top(input s, d, output a);
+	assign a = s ? a : d;
+endmodule
+EOT
+simplemap
+muxcover -mux4 -mux8
+select -assert-count 1 t:$_MUX_
+
+design -reset
+read_verilog <<EOT
+module top(input [3:0] s, input [3:0] d, output a);
+	wire b = s[1] ? a : d[1];
+	wire c = s[2] ? d[2] : d[3];
+	wire e = s[3] ? b : c;
+	assign a = s[0] ? e : d[0];
+endmodule
+EOT
+simplemap
+muxcover -mux4 -mux8
+select -assert-count 4 t:$_MUX_
+select -assert-none t:$_MUX4_ t:$_MUX8_
+
+design -reset
+read_verilog <<EOT
+module top(input s, a, b, c, output y);
+	wire m = y ? b : a;
+	assign y = s ? c : m;
+endmodule
+EOT
+simplemap
+muxcover -mux4=1 -dmux=0
+select -assert-count 1 t:$_MUX4_
+select -assert-count 1 t:$_MUX4_ %co:+[Y] t:$_MUX4_ %ci:+[S] %i w:* %i
+select -assert-none t:$_MUX_