From d493a55025c4defe19090e0ae38cc0290a9c9101 Mon Sep 17 00:00:00 2001 From: William Zhu Date: Thu, 27 Mar 2025 12:40:41 -0700 Subject: [PATCH] forgot to add some things to previous commit --- tests/silimate/opt_expand.ys | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/tests/silimate/opt_expand.ys b/tests/silimate/opt_expand.ys index d56078f1e..420785300 100644 --- a/tests/silimate/opt_expand.ys +++ b/tests/silimate/opt_expand.ys @@ -15,10 +15,15 @@ module top ( endmodule EOF check -assert + +# Check equivalence after opt_expand equiv_opt -assert opt_expand + +# Check final design has correct number of gates design -load postopt select -assert-count 2 t:$and select -assert-count 1 t:$or + design -reset log -pop @@ -38,7 +43,11 @@ module top ( endmodule EOF check -assert + +# Check equivalence after opt_expand equiv_opt -assert opt_expand + +# Check final design has correct number of gates design -load postopt select -assert-count 2 t:$and select -assert-count 1 t:$or @@ -62,7 +71,11 @@ module top ( endmodule EOF check -assert + +# Check equivalence after opt_expand equiv_opt -assert opt_expand + +# Check final design has correct number of gates design -load postopt select -assert-count 2 t:$and select -assert-count 1 t:$or @@ -89,7 +102,11 @@ module top ( endmodule EOF check -assert + +# Check equivalence after opt_expand equiv_opt -assert opt_expand + +# Check final design has correct number of gates design -load postopt select -assert-count 1 t:$and select -assert-count 1 t:$or @@ -114,7 +131,11 @@ module top ( endmodule EOF check -assert + +# Check equivalence after opt_expand equiv_opt -assert opt_expand + +# Check final design has correct number of gates design -load postopt select -assert-count 3 t:$and select -assert-count 1 t:$or @@ -139,7 +160,11 @@ module top ( endmodule EOF check -assert + +# Check equivalence after opt_expand equiv_opt -assert opt_expand + +# Check final design has correct number of gates design -load postopt select -assert-count 3 t:$and select -assert-count 2 t:$or @@ -163,7 +188,11 @@ module top ( endmodule EOF check -assert + +# Check equivalence after opt_expand equiv_opt -assert opt_expand + +# Check final design has correct number of gates design -load postopt select -assert-count 2 t:$and select -assert-count 1 t:$or @@ -189,7 +218,11 @@ module top ( endmodule EOF check -assert + +# Check equivalence after opt_expand equiv_opt -assert opt_expand + +# Check final design has correct number of gates design -load postopt select -assert-count 4 t:$and select -assert-count 2 t:$or @@ -216,7 +249,11 @@ module top ( endmodule EOF check -assert + +# Check equivalence after opt_expand equiv_opt -assert opt_expand + +# Check final design has correct number of gates design -load postopt select -assert-count 4 t:$and select -assert-count 3 t:$or