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fixup! opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped

This commit is contained in:
Emil J. Tywoniak 2026-03-25 12:39:33 +01:00
parent e3edd1501e
commit d33d048874
1 changed files with 8 additions and 3 deletions
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11
passes/opt/opt_expr.cc
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@ -1213,7 +1213,7 @@ skip_fine_alu:
} }
} }
if (!keepdc && cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex)))
{ {
RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B); RTLIL::SigSpec b = cell->getPort(ID::B);
@ -1235,8 +1235,13 @@ skip_fine_alu:
replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y); replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y);
goto next_cell; goto next_cell;
} }
if (a[i] == b[i]) if (keepdc) {
continue; if (!a[i].is_wire() && !b[i].is_wire() && a[i].data != RTLIL::State::Sx && b[i].data != RTLIL::State::Sx && a[i] == b[i])
continue;
} else {
if (a[i] == b[i])
continue;
}
new_a.append(a[i]); new_a.append(a[i]);
new_b.append(b[i]); new_b.append(b[i]);
} }