From d33d0488747c61142483e2af6793b04af17acf3d Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 25 Mar 2026 12:39:33 +0100 Subject: [PATCH] fixup! opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped --- passes/opt/opt_expr.cc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 829ae09cf..7c8684482 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1213,7 +1213,7 @@ skip_fine_alu: } } - if (!keepdc && cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) + if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) { RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec b = cell->getPort(ID::B); @@ -1235,8 +1235,13 @@ skip_fine_alu: replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y); goto next_cell; } - if (a[i] == b[i]) - continue; + if (keepdc) { + if (!a[i].is_wire() && !b[i].is_wire() && a[i].data != RTLIL::State::Sx && b[i].data != RTLIL::State::Sx && a[i] == b[i]) + continue; + } else { + if (a[i] == b[i]) + continue; + } new_a.append(a[i]); new_b.append(b[i]); }