From c50290fdab49f19c59cfbe15ba37b9782d6a71e4 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 27 Jul 2026 22:08:39 +0200
Subject: [PATCH] dfflibmap: fix formal verilog test so that it actually maps
 all flops

---
 tests/techmap/dfflibmap_proc_formal.ys | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/techmap/dfflibmap_proc_formal.ys b/tests/techmap/dfflibmap_proc_formal.ys
index 851238474..c687ff507 100644
--- a/tests/techmap/dfflibmap_proc_formal.ys
+++ b/tests/techmap/dfflibmap_proc_formal.ys
@@ -44,6 +44,7 @@ EOT
 
 proc
 opt
+techmap
 copy top top_unmapped
 design -save start