Merge pull request #6185 from YosysHQ/release/v0.69

Release version 0.69

CHANGELOG

@@ -2,12 +2,27 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.68 .. Yosys 0.69-dev
+Yosys 0.69 .. Yosys 0.70-dev
 --------------------------
 
+Yosys 0.68 .. Yosys 0.69
+--------------------------
+ * Commands and options
+    - Removed sum of products related parameters from
+      "abc" pass.
+    - Removed coolrunner2 and greenpak4 synthesis and related
+      passes.
+    - Removed "nlutmap" pass.
+    - Removed "-retime", "-noabc9", "-abc2" and "-abc" options
+      from synthesis passes.
+    - Removed "-[no]stderr" from "logger" pass.
+
+ * Various
+    - verific: Added "-sv2023" flag option to support System
+      Verilog 2023.
+
 Yosys 0.67 .. Yosys 0.68
 --------------------------
-
  * New commands and options
     - Added "symfpu" and "symfpu_convert" passes.
     - Removed "-fast" option from "abc" pass.

backends/verilog/verilog_backend.cc

@@ -677,7 +677,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
 				dump_sigspec(os, port.srst);
 				os << stringf(") begin\n");
 				clk_to_lof_body[clk_domain_str].push_back(os.str());
-				
+
 				std::ostringstream os2;
 				os2 << stringf("%s" "%s <= ", indent, temp_id);
 				dump_sigspec(os2, port.srst_value);

cmake/YosysVersionData.cmake

@@ -1,2 +1,2 @@
 set(YOSYS_VERSION_MAJOR 0)
-set(YOSYS_VERSION_MINOR 68)
+set(YOSYS_VERSION_MINOR 69)

docs/source/conf.py

@@ -6,7 +6,7 @@ import os
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2026 YosysHQ GmbH'
-yosys_ver = "0.68"
+yosys_ver = "0.69"
 
 # select HTML theme
 html_theme = 'furo-ys'

tests/techmap/dlatchlibmap_dlatchn.lib

@@ -4,7 +4,7 @@ library(test) {
     latch("IQ", "IQN") {
       data_in : "D";
       enable : "!ENA";
-    } 
+    }
     pin(D) {
       direction : input;
     }
@@ -18,6 +18,6 @@ library(test) {
     pin(QN) {
       direction: output;
       function : "IQN";
-    } 
+    }
   }
 }

tests/techmap/dlatchlibmap_dlatchsr_not_data.lib

@@ -24,4 +24,4 @@ library (test_not_data) {
       preset : "!RN";
     }
   }
-}
+}