From 9f75ca1f9834a39a863915b5dae0c7b1e33533bc Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 9 Sep 2026 07:26:44 +0200 Subject: [PATCH 1/2] Release version 0.69 --- CHANGELOG | 16 ++++++++++++++-- backends/verilog/verilog_backend.cc | 2 +- cmake/YosysVersionData.cmake | 2 +- docs/source/conf.py | 2 +- tests/lut/lut.sh | 0 tests/techmap/dlatchlibmap_dlatchn.lib | 4 ++-- tests/techmap/dlatchlibmap_dlatchsr_not_data.lib | 2 +- 7 files changed, 20 insertions(+), 8 deletions(-) mode change 100755 => 100644 tests/lut/lut.sh diff --git a/CHANGELOG b/CHANGELOG index b3bc5d0cd..ce32d9a1d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,12 +2,24 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.68 .. Yosys 0.69-dev +Yosys 0.68 .. Yosys 0.69 -------------------------- + * Commands and options + - Removed sum of products related parameters from + "abc" pass. + - Removed coolrunner2 and greenpak4 synthesis and related + passes. + - Removed "nlutmap" pass. + - Removed "-retime", "-noabc9", "-abc2" and "-abc" options + from synthesis passes. + - Removed "-[no]stderr" from "logger" pass. + + * Various + - verific: Added "-sv2023" flag option to support System + Verilog 2023. Yosys 0.67 .. Yosys 0.68 -------------------------- - * New commands and options - Added "symfpu" and "symfpu_convert" passes. - Removed "-fast" option from "abc" pass. diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index f23742913..cd54522cb 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -677,7 +677,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) dump_sigspec(os, port.srst); os << stringf(") begin\n"); clk_to_lof_body[clk_domain_str].push_back(os.str()); - + std::ostringstream os2; os2 << stringf("%s" "%s <= ", indent, temp_id); dump_sigspec(os2, port.srst_value); diff --git a/cmake/YosysVersionData.cmake b/cmake/YosysVersionData.cmake index d1b7ce109..0d25f07df 100644 --- a/cmake/YosysVersionData.cmake +++ b/cmake/YosysVersionData.cmake @@ -1,2 +1,2 @@ set(YOSYS_VERSION_MAJOR 0) -set(YOSYS_VERSION_MINOR 68) +set(YOSYS_VERSION_MINOR 69) diff --git a/docs/source/conf.py b/docs/source/conf.py index 4a423ae0c..0913d34db 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -6,7 +6,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2026 YosysHQ GmbH' -yosys_ver = "0.68" +yosys_ver = "0.69" # select HTML theme html_theme = 'furo-ys' diff --git a/tests/lut/lut.sh b/tests/lut/lut.sh old mode 100755 new mode 100644 diff --git a/tests/techmap/dlatchlibmap_dlatchn.lib b/tests/techmap/dlatchlibmap_dlatchn.lib index 5c04f179d..a7395edc0 100644 --- a/tests/techmap/dlatchlibmap_dlatchn.lib +++ b/tests/techmap/dlatchlibmap_dlatchn.lib @@ -4,7 +4,7 @@ library(test) { latch("IQ", "IQN") { data_in : "D"; enable : "!ENA"; - } + } pin(D) { direction : input; } @@ -18,6 +18,6 @@ library(test) { pin(QN) { direction: output; function : "IQN"; - } + } } } diff --git a/tests/techmap/dlatchlibmap_dlatchsr_not_data.lib b/tests/techmap/dlatchlibmap_dlatchsr_not_data.lib index dc35e05d4..8ceef3b7e 100644 --- a/tests/techmap/dlatchlibmap_dlatchsr_not_data.lib +++ b/tests/techmap/dlatchlibmap_dlatchsr_not_data.lib @@ -24,4 +24,4 @@ library (test_not_data) { preset : "!RN"; } } -} \ No newline at end of file +} From 5c7b22f37d1ee31dc1a5fb7c3d5a908510fb0bc8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 9 Sep 2026 08:00:21 +0200 Subject: [PATCH 2/2] Next dev cycle --- CHANGELOG | 3 +++ 1 file changed, 3 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index ce32d9a1d..74a187586 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.69 .. Yosys 0.70-dev +-------------------------- + Yosys 0.68 .. Yosys 0.69 -------------------------- * Commands and options