mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #5753 from YosysHQ/nella/carry-save-adders
Add Carry-save adders
This commit is contained in:
nella
GitHub
commit
413169663d
1
Makefile
1
Makefile
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@ -953,6 +953,7 @@ MK_TEST_DIRS += tests/verilog
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# Tests that don't generate .mk
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SH_TEST_DIRS =
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SH_TEST_DIRS += tests/arith_tree
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SH_TEST_DIRS += tests/simple
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SH_TEST_DIRS += tests/simple_abc9
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SH_TEST_DIRS += tests/hana
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@ -0,0 +1,112 @@
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/**
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* Wallace tree utilities for multi-operand addition using carry-save adders
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*
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* Terminology:
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* - compressor: $fa viewed as reducing 3 inputs to 2 outputs (sum + shifted carry) (3:2 compressor)
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* - level: A stage of parallel compression operations
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* - depth: Maximum number of 3:2 compressor levels from any input to a signal
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*
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* References:
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* - "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
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* - "A Suggestion for a Fast Multiplier" (https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Arithmetic/Wallace_mult.pdf)
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*/
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#ifndef WALLACE_TREE_H
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#define WALLACE_TREE_H
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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inline std::pair<SigSpec, SigSpec> emit_fa(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
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{
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SigSpec sum = module->addWire(NEW_ID, width);
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SigSpec cout = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, a, b, c, cout, sum);
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SigSpec carry;
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carry.append(State::S0);
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carry.append(cout.extract(0, width - 1));
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return {sum, carry};
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}
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/**
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* wallace_reduce_scheduled() - Reduce multiple operands to two using a Wallace tree
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* @module: The Yosys module to which the compressors will be added
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* @sigs: Vector of input signals (operands) to be reduced
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* @width: Target bit-width to which all operands will be zero-extended
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* @compressor_count: Optional pointer to return the number of $fa cells emitted
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*
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* Return: The final two reduced operands, that are to be fed into an adder
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*/
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inline std::pair<SigSpec, SigSpec> wallace_reduce_scheduled(Module *module, std::vector<SigSpec> &sigs, int width, int *compressor_count = nullptr)
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{
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struct DepthSig {
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SigSpec sig;
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int depth;
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};
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for (auto &s : sigs)
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s.extend_u0(width);
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std::vector<DepthSig> operands;
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operands.reserve(sigs.size());
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for (auto &s : sigs)
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operands.push_back({s, 0});
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// Number of $fa's emitted
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if (compressor_count)
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*compressor_count = 0;
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// Only compress operands ready at current level
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for (int level = 0; operands.size() > 2; level++) {
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// Partition operands into ready and waiting
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std::vector<DepthSig> ready, waiting;
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for (auto &op : operands) {
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if (op.depth <= level)
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ready.push_back(op);
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else
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waiting.push_back(op);
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}
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if (ready.size() < 3)
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continue;
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// Apply compressors to ready operands
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std::vector<DepthSig> compressed;
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size_t i = 0;
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while (i + 2 < ready.size()) {
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auto [sum, carry] = emit_fa(module, ready[i].sig, ready[i + 1].sig, ready[i + 2].sig, width);
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int new_depth = std::max({ready[i].depth, ready[i + 1].depth, ready[i + 2].depth}) + 1;
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compressed.push_back({sum, new_depth});
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compressed.push_back({carry, new_depth});
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if (compressor_count)
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(*compressor_count)++;
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i += 3;
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}
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// Uncompressed operands pass through to next level
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for (; i < ready.size(); i++)
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compressed.push_back(ready[i]);
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// Merge compressed with waiting operands
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for (auto &op : waiting)
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compressed.push_back(op);
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operands = std::move(compressed);
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}
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if (operands.size() == 0)
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return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
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else if (operands.size() == 1)
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return {operands[0].sig, SigSpec(State::S0, width)};
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else {
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log_assert(operands.size() == 2);
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log(" Wallace tree depth: %d levels of $fa + 1 final $add\n", std::max(operands[0].depth, operands[1].depth));
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return {operands[0].sig, operands[1].sig};
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}
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}
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YOSYS_NAMESPACE_END
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#endif
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@ -55,6 +55,7 @@ OBJS += passes/techmap/extractinv.o
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OBJS += passes/techmap/cellmatch.o
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OBJS += passes/techmap/clockgate.o
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OBJS += passes/techmap/constmap.o
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OBJS += passes/techmap/arith_tree.o
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endif
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ifeq ($(DISABLE_SPAWN),0)
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@ -0,0 +1,426 @@
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/**
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* Replaces chains of $add/$sub and $macc cells with carry-save adder trees
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*
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* Terminology:
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* - parent: Cells that consume another cell's output
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* - chainable: Adds/subs with no carry-out usage
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* - chain: Connected path of chainable cells
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*/
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#include "kernel/macc.h"
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#include "kernel/sigtools.h"
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#include "kernel/wallace_tree.h"
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#include "kernel/yosys.h"
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#include <queue>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Operand {
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SigSpec sig;
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bool is_signed;
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bool negate;
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};
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struct Traversal {
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SigMap sigmap;
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dict<SigBit, pool<Cell *>> bit_consumers;
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dict<SigBit, int> fanout;
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Traversal(Module *module) : sigmap(module)
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{
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for (auto cell : module->cells())
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for (auto &conn : cell->connections())
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_consumers[bit].insert(cell);
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for (auto &pair : bit_consumers)
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fanout[pair.first] = pair.second.size();
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for (auto wire : module->wires())
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if (wire->port_output)
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for (auto bit : sigmap(SigSpec(wire)))
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fanout[bit]++;
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}
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};
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struct Cells {
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pool<Cell *> addsub;
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pool<Cell *> alu;
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pool<Cell *> macc;
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static bool is_addsub(Cell *cell) { return cell->type == ID($add) || cell->type == ID($sub); }
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static bool is_alu(Cell *cell) { return cell->type == ID($alu); }
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static bool is_macc(Cell *cell) { return cell->type == ID($macc) || cell->type == ID($macc_v2); }
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bool empty() { return addsub.empty() && alu.empty() && macc.empty(); }
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Cells(Module *module)
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{
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for (auto cell : module->cells()) {
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if (is_addsub(cell))
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addsub.insert(cell);
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else if (is_alu(cell))
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alu.insert(cell);
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else if (is_macc(cell))
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macc.insert(cell);
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}
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}
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};
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struct AluInfo {
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Cells &cells;
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Traversal &traversal;
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bool is_subtract(Cell *cell)
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{
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SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
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SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
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return GetSize(bi) == 1 && bi[0] == State::S1 && GetSize(ci) == 1 && ci[0] == State::S1;
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}
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bool is_add(Cell *cell)
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{
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SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
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SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
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return GetSize(bi) == 1 && bi[0] == State::S0 && GetSize(ci) == 1 && ci[0] == State::S0;
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}
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bool is_chainable(Cell *cell)
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{
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if (!(is_add(cell) || is_subtract(cell)))
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return false;
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for (auto bit : traversal.sigmap(cell->getPort(ID::X)))
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if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0)
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return false;
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for (auto bit : traversal.sigmap(cell->getPort(ID::CO)))
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if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0)
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return false;
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return true;
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}
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};
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struct Rewriter {
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Module *module;
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Cells &cells;
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Traversal traversal;
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AluInfo alu_info;
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Rewriter(Module *module, Cells &cells) : module(module), cells(cells), traversal(module), alu_info{cells, traversal} {}
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Cell *sole_chainable_consumer(SigSpec sig, const pool<Cell *> &candidates)
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{
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Cell *consumer = nullptr;
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for (auto bit : sig) {
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if (!traversal.fanout.count(bit) || traversal.fanout[bit] != 1)
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return nullptr;
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if (!traversal.bit_consumers.count(bit) || traversal.bit_consumers[bit].size() != 1)
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return nullptr;
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Cell *c = *traversal.bit_consumers[bit].begin();
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if (!candidates.count(c))
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return nullptr;
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if (consumer == nullptr)
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consumer = c;
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else if (consumer != c)
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return nullptr;
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}
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return consumer;
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}
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dict<Cell *, Cell *> find_parents(const pool<Cell *> &candidates)
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{
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dict<Cell *, Cell *> parent_of;
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for (auto cell : candidates) {
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Cell *consumer = sole_chainable_consumer(traversal.sigmap(cell->getPort(ID::Y)), candidates);
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if (consumer && consumer != cell)
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parent_of[cell] = consumer;
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}
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return parent_of;
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}
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std::pair<dict<Cell *, pool<Cell *>>, pool<Cell *>> invert_parent_map(const dict<Cell *, Cell *> &parent_of)
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{
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dict<Cell *, pool<Cell *>> children_of;
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pool<Cell *> has_parent;
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for (auto &[child, parent] : parent_of) {
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children_of[parent].insert(child);
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has_parent.insert(child);
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}
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return {children_of, has_parent};
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}
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pool<Cell *> collect_chain(Cell *root, const dict<Cell *, pool<Cell *>> &children_of)
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{
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pool<Cell *> chain;
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std::queue<Cell *> q;
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q.push(root);
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while (!q.empty()) {
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Cell *cur = q.front();
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q.pop();
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if (!chain.insert(cur).second)
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continue;
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auto it = children_of.find(cur);
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if (it != children_of.end())
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for (auto child : it->second)
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q.push(child);
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}
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return chain;
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}
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pool<SigBit> internal_bits(const pool<Cell *> &chain)
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{
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pool<SigBit> bits;
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for (auto cell : chain)
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for (auto bit : traversal.sigmap(cell->getPort(ID::Y)))
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bits.insert(bit);
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return bits;
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}
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static bool overlaps(SigSpec sig, const pool<SigBit> &bits)
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{
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for (auto bit : sig)
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if (bits.count(bit))
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return true;
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return false;
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}
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bool feeds_subtracted_port(Cell *child, Cell *parent)
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{
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bool parent_subtracts;
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if (parent->type == ID($sub))
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parent_subtracts = true;
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else if (cells.is_alu(parent))
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parent_subtracts = alu_info.is_subtract(parent);
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else
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return false;
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if (!parent_subtracts)
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return false;
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// Check if any bit of child's Y connects to parent's B
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SigSpec child_y = traversal.sigmap(child->getPort(ID::Y));
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SigSpec parent_b = traversal.sigmap(parent->getPort(ID::B));
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for (auto bit : child_y)
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for (auto pbit : parent_b)
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if (bit == pbit)
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return true;
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return false;
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}
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std::vector<Operand> extract_chain_operands(const pool<Cell *> &chain, Cell *root, const dict<Cell *, Cell *> &parent_of, int &neg_compensation)
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{
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pool<SigBit> chain_bits = internal_bits(chain);
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// Propagate negation flags through chain
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dict<Cell *, bool> negated;
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negated[root] = false;
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{
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std::queue<Cell *> q;
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q.push(root);
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while (!q.empty()) {
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Cell *cur = q.front();
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q.pop();
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for (auto cell : chain) {
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if (!parent_of.count(cell) || parent_of.at(cell) != cur)
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continue;
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if (negated.count(cell))
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continue;
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negated[cell] = negated[cur] ^ feeds_subtracted_port(cell, cur);
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q.push(cell);
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}
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}
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}
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// Extract leaf operands
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std::vector<Operand> operands;
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neg_compensation = 0;
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for (auto cell : chain) {
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bool cell_neg = negated.count(cell) ? negated[cell] : false;
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SigSpec a = traversal.sigmap(cell->getPort(ID::A));
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SigSpec b = traversal.sigmap(cell->getPort(ID::B));
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bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
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bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
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bool b_sub = (cell->type == ID($sub)) || (cells.is_alu(cell) && alu_info.is_subtract(cell));
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// Only add operands not produced by other chain cells
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if (!overlaps(a, chain_bits)) {
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operands.push_back({a, a_signed, cell_neg});
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if (cell_neg)
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neg_compensation++;
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}
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if (!overlaps(b, chain_bits)) {
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bool neg = cell_neg ^ b_sub;
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operands.push_back({b, b_signed, neg});
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if (neg)
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neg_compensation++;
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}
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}
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return operands;
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}
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bool extract_macc_operands(Cell *cell, std::vector<Operand> &operands, int &neg_compensation)
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{
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Macc macc(cell);
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neg_compensation = 0;
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for (auto &term : macc.terms) {
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// Bail on multiplication
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if (GetSize(term.in_b) != 0)
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return false;
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operands.push_back({term.in_a, term.is_signed, term.do_subtract});
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if (term.do_subtract)
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neg_compensation++;
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}
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return true;
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}
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SigSpec extend_operand(SigSpec sig, bool is_signed, int width)
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{
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if (GetSize(sig) < width) {
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SigBit pad;
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if (is_signed && GetSize(sig) > 0)
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pad = sig[GetSize(sig) - 1];
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else
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pad = State::S0;
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sig.append(SigSpec(pad, width - GetSize(sig)));
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}
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if (GetSize(sig) > width)
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sig = sig.extract(0, width);
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return sig;
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}
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void replace_with_carry_save_tree(std::vector<Operand> &operands, SigSpec result_y, int neg_compensation, const char *desc)
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{
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int width = GetSize(result_y);
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std::vector<SigSpec> extended;
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extended.reserve(operands.size() + 1);
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for (auto &op : operands) {
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SigSpec s = extend_operand(op.sig, op.is_signed, width);
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if (op.negate)
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s = module->Not(NEW_ID, s);
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extended.push_back(s);
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}
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// Add correction for negated operands (-x = ~x + 1 so 1 per negation)
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if (neg_compensation > 0)
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extended.push_back(SigSpec(neg_compensation, width));
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int compressor_count;
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auto [a, b] = wallace_reduce_scheduled(module, extended, width, &compressor_count);
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log(" %s -> %d $fa + 1 $add (%d operands, module %s)\n", desc, compressor_count, (int)operands.size(), log_id(module));
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// Emit final add
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module->addAdd(NEW_ID, a, b, result_y, false);
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}
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void process_chains()
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{
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pool<Cell *> candidates;
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for (auto cell : cells.addsub)
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candidates.insert(cell);
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for (auto cell : cells.alu)
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if (alu_info.is_chainable(cell))
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candidates.insert(cell);
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if (candidates.empty())
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return;
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|
||||
auto parent_of = find_parents(candidates);
|
||||
auto [children_of, has_parent] = invert_parent_map(parent_of);
|
||||
|
||||
pool<Cell *> to_remove;
|
||||
for (auto root : candidates) {
|
||||
if (has_parent.count(root) || to_remove.count(root))
|
||||
continue; // Not a tree root
|
||||
|
||||
pool<Cell *> chain = collect_chain(root, children_of);
|
||||
if (chain.size() < 2)
|
||||
continue;
|
||||
|
||||
int neg_compensation;
|
||||
auto operands = extract_chain_operands(chain, root, parent_of, neg_compensation);
|
||||
if (operands.size() < 3)
|
||||
continue;
|
||||
|
||||
for (auto c : chain)
|
||||
to_remove.insert(c);
|
||||
|
||||
replace_with_carry_save_tree(operands, root->getPort(ID::Y), neg_compensation, "Replaced add/sub chain");
|
||||
}
|
||||
|
||||
for (auto cell : to_remove)
|
||||
module->remove(cell);
|
||||
}
|
||||
|
||||
void process_maccs()
|
||||
{
|
||||
for (auto cell : cells.macc) {
|
||||
std::vector<Operand> operands;
|
||||
int neg_compensation;
|
||||
if (!extract_macc_operands(cell, operands, neg_compensation))
|
||||
continue;
|
||||
if (operands.size() < 3)
|
||||
continue;
|
||||
|
||||
replace_with_carry_save_tree(operands, cell->getPort(ID::Y), neg_compensation, "Replaced $macc");
|
||||
module->remove(cell);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
void run(Module *module)
|
||||
{
|
||||
Cells cells(module);
|
||||
|
||||
if (cells.empty())
|
||||
return;
|
||||
|
||||
Rewriter rewriter{module, cells};
|
||||
rewriter.process_chains();
|
||||
rewriter.process_maccs();
|
||||
}
|
||||
|
||||
struct ArithTreePass : public Pass {
|
||||
ArithTreePass() : Pass("arith_tree", "convert add/sub/macc chains to carry-save adder trees") {}
|
||||
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" arith_tree [selection]\n");
|
||||
log("\n");
|
||||
log("This pass replaces chains of $add/$sub cells, $alu cells (with constant\n");
|
||||
log("BI/CI), and $macc/$macc_v2 cells (without multiplications) with carry-save\n");
|
||||
log("adder trees using $fa cells and a single final $add.\n");
|
||||
log("\n");
|
||||
log("The tree uses Wallace-tree scheduling: at each level, ready operands are\n");
|
||||
log("grouped into triplets and compressed via full adders, giving\n");
|
||||
log("O(log_{1.5} N) depth for N input operands.\n");
|
||||
log("\n");
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing ARITH_TREE pass.\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
break;
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
run(module);
|
||||
}
|
||||
}
|
||||
} ArithTreePass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -58,6 +58,7 @@ synth -top my_design -booth
|
|||
#include "kernel/sigtools.h"
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/macc.h"
|
||||
#include "kernel/wallace_tree.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
|
@ -317,36 +318,6 @@ struct BoothPassWorker {
|
|||
}
|
||||
}
|
||||
|
||||
SigSig WallaceSum(int width, std::vector<SigSpec> summands)
|
||||
{
|
||||
for (auto &s : summands)
|
||||
s.extend_u0(width);
|
||||
|
||||
while (summands.size() > 2) {
|
||||
std::vector<SigSpec> new_summands;
|
||||
int i;
|
||||
for (i = 0; i < (int) summands.size() - 2; i += 3) {
|
||||
SigSpec x = module->addWire(NEW_ID, width);
|
||||
SigSpec y = module->addWire(NEW_ID, width);
|
||||
BuildBitwiseFa(module, NEW_ID.str(), summands[i], summands[i + 1],
|
||||
summands[i + 2], x, y);
|
||||
new_summands.push_back(y);
|
||||
new_summands.push_back({x.extract(0, width - 1), State::S0});
|
||||
}
|
||||
|
||||
new_summands.insert(new_summands.begin(), summands.begin() + i, summands.end());
|
||||
|
||||
std::swap(summands, new_summands);
|
||||
}
|
||||
|
||||
if (!summands.size())
|
||||
return SigSig(SigSpec(width, State::S0), SigSpec(width, State::S0));
|
||||
else if (summands.size() == 1)
|
||||
return SigSig(summands[0], SigSpec(width, State::S0));
|
||||
else
|
||||
return SigSig(summands[0], summands[1]);
|
||||
}
|
||||
|
||||
/*
|
||||
Build Multiplier.
|
||||
-------------------------
|
||||
|
|
@ -415,16 +386,16 @@ struct BoothPassWorker {
|
|||
// Later on yosys will clean up unused constants
|
||||
// DebugDumpAlignPP(aligned_pp);
|
||||
|
||||
SigSig wtree_sum = WallaceSum(z_sz, aligned_pp);
|
||||
auto [wtree_a, wtree_b] = wallace_reduce_scheduled(module, aligned_pp, z_sz);
|
||||
|
||||
// Debug code: Dump out the csa trees
|
||||
// DumpCSATrees(debug_csa_trees);
|
||||
// Build the CPA to do the final accumulation.
|
||||
log_assert(wtree_sum.second[0] == State::S0);
|
||||
log_assert(wtree_b[0] == State::S0);
|
||||
if (mapped_cpa)
|
||||
BuildCPA(module, wtree_sum.first, {State::S0, wtree_sum.second.extract_end(1)}, Z);
|
||||
BuildCPA(module, wtree_a, wtree_b, Z);
|
||||
else
|
||||
module->addAdd(NEW_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z);
|
||||
module->addAdd(NEW_ID, wtree_a, wtree_b, Z);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -67,6 +67,10 @@ struct SynthPass : public ScriptPass {
|
|||
log(" -booth\n");
|
||||
log(" run the booth pass to map $mul to Booth encoded multipliers\n");
|
||||
log("\n");
|
||||
log(" -arith_tree\n");
|
||||
log(" run the arith_tree pass to convert $add/$sub chains and $macc cells to\n");
|
||||
log(" carry-save adder trees.\n");
|
||||
log("\n");
|
||||
log(" -noalumacc\n");
|
||||
log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
|
||||
log(" their direct form ($add, $sub, etc.).\n");
|
||||
|
|
@ -108,7 +112,7 @@ struct SynthPass : public ScriptPass {
|
|||
}
|
||||
|
||||
string top_module, fsm_opts, memory_opts, abc;
|
||||
bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt, relative_share;
|
||||
bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, arith_tree, hieropt, relative_share;
|
||||
int lut;
|
||||
std::vector<std::string> techmap_maps;
|
||||
|
||||
|
|
@ -127,6 +131,7 @@ struct SynthPass : public ScriptPass {
|
|||
noshare = false;
|
||||
flowmap = false;
|
||||
booth = false;
|
||||
arith_tree = false;
|
||||
hieropt = false;
|
||||
relative_share = false;
|
||||
abc = "abc";
|
||||
|
|
@ -187,7 +192,10 @@ struct SynthPass : public ScriptPass {
|
|||
booth = true;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (args[argidx] == "-arith_tree") {
|
||||
arith_tree = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nordff") {
|
||||
memory_opts += " -nordff";
|
||||
continue;
|
||||
|
|
@ -289,6 +297,8 @@ struct SynthPass : public ScriptPass {
|
|||
run("booth", " (if -booth)");
|
||||
if (!noalumacc)
|
||||
run("alumacc", " (unless -noalumacc)");
|
||||
if (arith_tree || help_mode)
|
||||
run("arith_tree", " (if -arith_tree)");
|
||||
if (!noshare)
|
||||
run("share", " (unless -noshare)");
|
||||
run("opt" + hieropt_flag);
|
||||
|
|
@ -301,7 +311,7 @@ struct SynthPass : public ScriptPass {
|
|||
run("memory_map");
|
||||
run("opt -full");
|
||||
if (help_mode) {
|
||||
run(techmap_cmd, " (unless -extra-map)");
|
||||
run(techmap_cmd, " (unless -extra-map)");
|
||||
run(techmap_cmd + " -map +/techmap.v -map <inject>", " (if -extra-map)");
|
||||
} else {
|
||||
std::string techmap_opts;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,197 @@
|
|||
read_verilog <<EOT
|
||||
module add3(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add5(
|
||||
input [11:0] a, b, c, d, e,
|
||||
output [11:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add8(
|
||||
input [15:0] a, b, c, d, e, f, g, h,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add16(
|
||||
input [15:0] a0, a1, a2, a3, a4, a5, a6, a7,
|
||||
input [15:0] a8, a9, a10, a11, a12, a13, a14, a15,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
|
||||
+ a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 14 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
module alu_add3(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
wire [7:0] tmp, x1, x2, co1, co2;
|
||||
// a + b
|
||||
$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
|
||||
alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp), .X(x1), .CO(co1));
|
||||
// tmp + c
|
||||
$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
|
||||
alu2 (.A(tmp), .B(c), .BI(1'b0), .CI(1'b0), .Y(y), .X(x2), .CO(co2));
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
select -assert-count 2 t:$alu
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
module alu_add4(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
wire [7:0] tmp1, tmp2, x1, x2, x3, co1, co2, co3;
|
||||
// a + b
|
||||
$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
|
||||
alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp1), .X(x1), .CO(co1));
|
||||
// c + d
|
||||
$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
|
||||
alu2 (.A(c), .B(d), .BI(1'b0), .CI(1'b0), .Y(tmp2), .X(x2), .CO(co2));
|
||||
// tmp1 + tmp2
|
||||
$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
|
||||
alu3 (.A(tmp1), .B(tmp2), .BI(1'b0), .CI(1'b0), .Y(y), .X(x3), .CO(co3));
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
select -assert-count 3 t:$alu
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
module alu_add5(
|
||||
input [11:0] a, b, c, d, e,
|
||||
output [11:0] y
|
||||
);
|
||||
wire [11:0] tmp1, tmp2, tmp3, x1, x2, x3, x4, co1, co2, co3, co4;
|
||||
// a + b
|
||||
$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
|
||||
alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp1), .X(x1), .CO(co1));
|
||||
// c + d
|
||||
$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
|
||||
alu2 (.A(c), .B(d), .BI(1'b0), .CI(1'b0), .Y(tmp2), .X(x2), .CO(co2));
|
||||
// tmp1 + tmp2
|
||||
$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
|
||||
alu3 (.A(tmp1), .B(tmp2), .BI(1'b0), .CI(1'b0), .Y(tmp3), .X(x3), .CO(co3));
|
||||
// tmp3 + e
|
||||
$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
|
||||
alu4 (.A(tmp3), .B(e), .BI(1'b0), .CI(1'b0), .Y(y), .X(x4), .CO(co4));
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
select -assert-count 4 t:$alu
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
design -reset
|
||||
|
||||
# Test $macc cells (alumacc+opt output)
|
||||
read_verilog <<EOT
|
||||
module macc_add3(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$macc t:$macc_v2 %u
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_add5(
|
||||
input [11:0] a, b, c, d, e,
|
||||
output [11:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$macc t:$macc_v2 %u
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_add8(
|
||||
input [15:0] a, b, c, d, e, f, g, h,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$macc t:$macc_v2 %u
|
||||
design -reset
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
read_verilog <<EOT
|
||||
module equiv_macc_add3(
|
||||
input [3:0] a, b, c,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_macc_add4(
|
||||
input [3:0] a, b, c, d,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_macc_add8(
|
||||
input [3:0] a, b, c, d, e, f, g, h,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_macc_signed(
|
||||
input signed [3:0] a, b, c, d,
|
||||
output signed [5:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_macc_sub_mixed(
|
||||
input [3:0] a, b, c, d,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b - c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-min 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_macc_sub_all(
|
||||
input [3:0] a, b, c, d,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a - b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-min 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
|
@ -0,0 +1,407 @@
|
|||
read_verilog <<EOT
|
||||
module add_1bit(
|
||||
input a, b, c,
|
||||
output [1:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_1bit_wide(
|
||||
input a, b, c, d,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_wide_out(
|
||||
input [7:0] a, b, c, d,
|
||||
output [31:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_mixed(
|
||||
input [7:0] a,
|
||||
input [3:0] b,
|
||||
input [15:0] c,
|
||||
input [7:0] d,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_signed(
|
||||
input signed [7:0] a, b, c, d,
|
||||
output signed [9:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_repeated(
|
||||
input [7:0] a,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + a + a + a;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_const(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b + c + 8'd42;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_two(
|
||||
input [7:0] a, b, c, d, e, f, g, h,
|
||||
output [7:0] y1, y2
|
||||
);
|
||||
assign y1 = a + b + c + d;
|
||||
assign y2 = e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 4 t:$fa
|
||||
select -assert-count 2 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module fir_4tap(
|
||||
input clk,
|
||||
input [15:0] x, c0, c1, c2, c3,
|
||||
output reg [31:0] y
|
||||
);
|
||||
reg [15:0] x1, x2, x3;
|
||||
always @(posedge clk) begin
|
||||
x1 <= x;
|
||||
x2 <= x1;
|
||||
x3 <= x2;
|
||||
end
|
||||
|
||||
wire [31:0] sum = x*c0 + x1*c1 + x2*c2 + x3*c3;
|
||||
always @(posedge clk) y <= sum;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module alu_add2(
|
||||
input [7:0] a, b,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-none t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-count 1 t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module alu_sub2(
|
||||
input [7:0] a, b,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-none t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-count 1 t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module alu_compare(
|
||||
input [7:0] a, b,
|
||||
output y
|
||||
);
|
||||
assign y = (a < b);
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-none t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-count 1 t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_mul(
|
||||
input [7:0] a, b, c,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a * b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$fa
|
||||
select -assert-min 1 t:$macc t:$macc_v2 %u
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module alu_fanout(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] mid, y
|
||||
);
|
||||
wire [7:0] ab = a + b;
|
||||
assign mid = ab;
|
||||
assign y = ab + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$fa
|
||||
select -assert-count 2 t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_2port(
|
||||
input [7:0] a, b,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$fa
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_mixed_width(
|
||||
input [7:0] a,
|
||||
input [3:0] b,
|
||||
input [15:0] c,
|
||||
input [7:0] d,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_signed(
|
||||
input signed [7:0] a, b, c, d,
|
||||
output signed [9:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module fir_4tap_macc(
|
||||
input clk,
|
||||
input [15:0] x, c0, c1, c2, c3,
|
||||
output reg [31:0] y
|
||||
);
|
||||
reg [15:0] x1, x2, x3;
|
||||
always @(posedge clk) begin
|
||||
x1 <= x;
|
||||
x2 <= x1;
|
||||
x3 <= x2;
|
||||
end
|
||||
|
||||
wire [31:0] sum = x*c0 + x1*c1 + x2*c2 + x3*c3;
|
||||
always @(posedge clk) y <= sum;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-min 1 t:$dff
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_mixed_sign(
|
||||
input signed [7:0] a,
|
||||
input [7:0] b,
|
||||
input signed [7:0] c,
|
||||
output signed [9:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_wide32(
|
||||
input [31:0] a, b, c, d,
|
||||
output [31:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module passthrough(
|
||||
input [7:0] a,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-none t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-none t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_mul_survives(
|
||||
input [7:0] a, b, c, d,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a * b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$fa
|
||||
select -assert-min 1 t:$macc t:$macc_v2 %u
|
||||
design -reset
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
read_verilog <<EOT
|
||||
module equiv_add3(
|
||||
input [3:0] a, b, c,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_add4(
|
||||
input [3:0] a, b, c, d,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_add5(
|
||||
input [3:0] a, b, c, d, e,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_add8(
|
||||
input [3:0] a, b, c, d, e, f, g, h,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_signed(
|
||||
input signed [3:0] a, b, c, d,
|
||||
output signed [5:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_mixed(
|
||||
input [1:0] a,
|
||||
input [3:0] b,
|
||||
input [5:0] c,
|
||||
output [5:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_sub_3op(
|
||||
input [3:0] a, b, c,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a - b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_sub_mixed(
|
||||
input [3:0] a, b, c, d,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b - c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-min 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_sub_all(
|
||||
input [3:0] a, b, c, d,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a - b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-min 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_sub_signed(
|
||||
input signed [3:0] a, b, c, d,
|
||||
output signed [5:0] y
|
||||
);
|
||||
assign y = a + b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_double_neg(
|
||||
input [3:0] a, b, c,
|
||||
output [3:0] y
|
||||
);
|
||||
wire [3:0] ab = a - b;
|
||||
assign y = c - ab;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
read_verilog <<EOT
|
||||
module add8(
|
||||
input [15:0] a, b, c, d, e, f, g, h,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
|
||||
arith_tree
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
|
||||
arith_tree
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_idempotent(
|
||||
input [15:0] a, b, c, d, e, f, g, h,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
|
||||
arith_tree
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-none t:$alu
|
||||
|
||||
arith_tree
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-none t:$alu
|
||||
design -reset
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
read_verilog <<EOT
|
||||
module add2(
|
||||
input [7:0] a, b,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_fanout(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] mid, y
|
||||
);
|
||||
wire [7:0] ab = a + b;
|
||||
assign mid = ab;
|
||||
assign y = ab + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub2(
|
||||
input [7:0] a, b,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-count 1 t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_multi_const(
|
||||
input [7:0] x,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = 8'd1 + 8'd2 + 8'd3 + x;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-max 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_partial(
|
||||
input [7:0] a, b, c, d, e,
|
||||
output [7:0] mid, y
|
||||
);
|
||||
wire [7:0] ab = a + b;
|
||||
assign mid = ab;
|
||||
assign y = ab + c + d + e;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 2 t:$add
|
||||
design -reset
|
||||
|
|
@ -0,0 +1,240 @@
|
|||
read_verilog <<EOT
|
||||
module sub_3op(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub_mixed(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b - c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub_all(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 3 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub_5op(
|
||||
input [11:0] a, b, c, d, e,
|
||||
output [11:0] y
|
||||
);
|
||||
assign y = a - b + c - d + e;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 4 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 2 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub_signed(
|
||||
input signed [7:0] a, b, c, d,
|
||||
output signed [9:0] y
|
||||
);
|
||||
assign y = a + b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 2 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub_double_neg(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
wire [7:0] ab = a - b;
|
||||
assign y = c - ab;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_sub_3op(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_sub_mixed2(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b - c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_sub_all(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_sub_signed(
|
||||
input signed [7:0] a, b, c, d,
|
||||
output signed [9:0] y
|
||||
);
|
||||
assign y = a + b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_sub_mixed(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b - c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$macc t:$macc_v2 %u
|
||||
select -assert-min 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_const(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b + c + 8'd42;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$macc t:$macc_v2 %u
|
||||
select -assert-min 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_two(
|
||||
input [7:0] a, b, c, d, e, f, g, h,
|
||||
output [7:0] y1, y2
|
||||
);
|
||||
assign y1 = a + b + c + d;
|
||||
assign y2 = e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$macc t:$macc_v2 %u
|
||||
select -assert-count 4 t:$fa
|
||||
select -assert-count 2 t:$add
|
||||
design -reset
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
set -e
|
||||
for x in *.ys; do
|
||||
echo "Running $x.."
|
||||
../../yosys -ql ${x%.ys}.log $x
|
||||
done
|
||||
Loading…
Reference in New Issue