Merge pull request #6239 from YosysHQ/emil/bufnorm-iopad-compat

Emil/bufnorm iopad compat
This commit is contained in:
Emil J
2026-09-23 10:11:31 +00:00
committed by GitHub
4 changed files with 59 additions and 3 deletions
+1 -3
View File
@@ -402,10 +402,8 @@ void RTLIL::Module::bufNormalize()
}
}
// If a wire has one or more inout drivers and an unconditional driver, that's still a conflict
for (auto driver : weakly_driven)
if (!driven.insert(driver).second)
conflicted.insert(driver);
driven.insert(driver);
// This only leaves the drivers matching `driven`'s definition above
for (auto driver : conflicted)
+21
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@@ -0,0 +1,21 @@
read_verilog <<EOT
module top(input i, output o);
wire t;
inpad u_in (.i(i), .o(t));
outpad u_out (.i(t), .o(o));
endmodule
module inpad(input i, output o);
IB ib (.I(i), .O(o));
endmodule
module outpad(input i, output o);
OB ob (.I(~i), .O(o));
endmodule
EOT
synth_lattice -family ecp5 -top top
hierarchy -check
check -assert
select -assert-count 2 t:TRELLIS_IO
select -assert-count 1 t:TRELLIS_IO %x:+[B] w:i %i
+18
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@@ -0,0 +1,18 @@
read_verilog <<EOT
(* blackbox *)
module pad(inout B, output O);
endmodule
module top(input i, output o);
wire a, b;
assign a = i;
assign b = i;
pad p (.B(a), .O(o));
endmodule
EOT
hierarchy -top top
abc_new -liberty ../liberty/normal.lib
clean
check -assert
select -assert-count 1 t:pad %x:+[B] w:i %i
+19
View File
@@ -0,0 +1,19 @@
read_verilog <<EOT
(* blackbox *)
module pad(inout B, output O);
endmodule
module top(input i, output o);
wire a, b;
assign a = i;
assign b = i;
pad p (.B(a), .O(o));
endmodule
EOT
hierarchy -top top
bufnorm -update
bufnorm -reset
clean
check -assert
select -assert-count 1 t:pad %x:+[B] w:i %i