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Merge pull request #6239 from YosysHQ/emil/bufnorm-iopad-compat
Emil/bufnorm iopad compat
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@@ -402,10 +402,8 @@ void RTLIL::Module::bufNormalize()
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}
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}
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// If a wire has one or more inout drivers and an unconditional driver, that's still a conflict
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for (auto driver : weakly_driven)
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if (!driven.insert(driver).second)
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conflicted.insert(driver);
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driven.insert(driver);
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// This only leaves the drivers matching `driven`'s definition above
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for (auto driver : conflicted)
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@@ -0,0 +1,21 @@
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read_verilog <<EOT
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module top(input i, output o);
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wire t;
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inpad u_in (.i(i), .o(t));
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outpad u_out (.i(t), .o(o));
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endmodule
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module inpad(input i, output o);
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IB ib (.I(i), .O(o));
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endmodule
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module outpad(input i, output o);
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OB ob (.I(~i), .O(o));
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endmodule
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EOT
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synth_lattice -family ecp5 -top top
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hierarchy -check
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check -assert
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select -assert-count 2 t:TRELLIS_IO
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select -assert-count 1 t:TRELLIS_IO %x:+[B] w:i %i
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@@ -0,0 +1,18 @@
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read_verilog <<EOT
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(* blackbox *)
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module pad(inout B, output O);
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endmodule
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module top(input i, output o);
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wire a, b;
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assign a = i;
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assign b = i;
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pad p (.B(a), .O(o));
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endmodule
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EOT
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hierarchy -top top
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abc_new -liberty ../liberty/normal.lib
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clean
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check -assert
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select -assert-count 1 t:pad %x:+[B] w:i %i
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@@ -0,0 +1,19 @@
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read_verilog <<EOT
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(* blackbox *)
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module pad(inout B, output O);
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endmodule
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module top(input i, output o);
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wire a, b;
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assign a = i;
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assign b = i;
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pad p (.B(a), .O(o));
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endmodule
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EOT
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hierarchy -top top
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bufnorm -update
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bufnorm -reset
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clean
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check -assert
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select -assert-count 1 t:pad %x:+[B] w:i %i
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