diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc
index aad4f5199..c43a3e9ca 100644
--- a/kernel/rtlil_bufnorm.cc
+++ b/kernel/rtlil_bufnorm.cc
@@ -402,10 +402,8 @@ void RTLIL::Module::bufNormalize()
 			}
 		}
 
-		// If a wire has one or more inout drivers and an unconditional driver, that's still a conflict
 		for (auto driver : weakly_driven)
-			if (!driven.insert(driver).second)
-				conflicted.insert(driver);
+			driven.insert(driver);
 
 		// This only leaves the drivers matching `driven`'s definition above
 		for (auto driver : conflicted)
diff --git a/tests/arch/ecp5/abc9_inout_pad_input.ys b/tests/arch/ecp5/abc9_inout_pad_input.ys
new file mode 100644
index 000000000..04fc54d14
--- /dev/null
+++ b/tests/arch/ecp5/abc9_inout_pad_input.ys
@@ -0,0 +1,21 @@
+read_verilog <<EOT
+module top(input i, output o);
+  wire t;
+  inpad u_in (.i(i), .o(t));
+  outpad u_out (.i(t), .o(o));
+endmodule
+
+module inpad(input i, output o);
+  IB ib (.I(i), .O(o));
+endmodule
+
+module outpad(input i, output o);
+  OB ob (.I(~i), .O(o));
+endmodule
+EOT
+
+synth_lattice -family ecp5 -top top
+hierarchy -check
+check -assert
+select -assert-count 2 t:TRELLIS_IO
+select -assert-count 1 t:TRELLIS_IO %x:+[B] w:i %i
diff --git a/tests/techmap/abc_new_inout_pad.ys b/tests/techmap/abc_new_inout_pad.ys
new file mode 100644
index 000000000..d586fd213
--- /dev/null
+++ b/tests/techmap/abc_new_inout_pad.ys
@@ -0,0 +1,18 @@
+read_verilog <<EOT
+(* blackbox *)
+module pad(inout B, output O);
+endmodule
+
+module top(input i, output o);
+  wire a, b;
+  assign a = i;
+  assign b = i;
+  pad p (.B(a), .O(o));
+endmodule
+EOT
+
+hierarchy -top top
+abc_new -liberty ../liberty/normal.lib
+clean
+check -assert
+select -assert-count 1 t:pad %x:+[B] w:i %i
diff --git a/tests/techmap/bufnorm_inout_input.ys b/tests/techmap/bufnorm_inout_input.ys
new file mode 100644
index 000000000..d9bcc8153
--- /dev/null
+++ b/tests/techmap/bufnorm_inout_input.ys
@@ -0,0 +1,19 @@
+read_verilog <<EOT
+(* blackbox *)
+module pad(inout B, output O);
+endmodule
+
+module top(input i, output o);
+  wire a, b;
+  assign a = i;
+  assign b = i;
+  pad p (.B(a), .O(o));
+endmodule
+EOT
+
+hierarchy -top top
+bufnorm -update
+bufnorm -reset
+clean
+check -assert
+select -assert-count 1 t:pad %x:+[B] w:i %i