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Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
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Akash Levy 2025-09-11 04:46:32 -07:00 committed by GitHub
parent b70aeea35c
commit 8f5b20c423
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1 changed files with 5 additions and 5 deletions
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10
tests/peepopt/addsub_c.ys
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@ -81,7 +81,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] add;
assign add = a + 4'sd6;
@ -100,7 +100,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] add;
assign add = a + 4'sd6;
@ -119,7 +119,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] sub;
assign sub = a - 4'sd6;
@ -138,7 +138,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] sub;
assign sub = a - 4'sd6;
@ -159,7 +159,7 @@ log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
output signed [7:0] y,
output signed [7:0] y
);
wire signed [7:0] add;
assign add = 4'sd6 + a;