From b1f4d0d8aa202984fe16c9cefb5db6f7e1b53ca8 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Thu, 11 Sep 2025 04:47:28 -0700
Subject: [PATCH] Small adjustments

---
 passes/opt/peepopt_addsub_c.pmg |  4 ++--
 tests/peepopt/addsub_c.ys       | 30 +++++++++++++++---------------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/passes/opt/peepopt_addsub_c.pmg b/passes/opt/peepopt_addsub_c.pmg
index 76c6bd74f..483fed4d1 100644
--- a/passes/opt/peepopt_addsub_c.pmg
+++ b/passes/opt/peepopt_addsub_c.pmg
@@ -1,7 +1,7 @@
 pattern addsub_c
 //
 // Authored by Akash Levy of Silimate, Inc. under ISC license.
-// Transforms add->add/sub_c into add_c canceling the constants out:
+// Transforms add->add/sub_c into add_c folding the constants:
 // y = (a +- b_const) +- c_const   ===>   a +- eval(b_const +- c_const)
 //
 
@@ -76,7 +76,7 @@ code
 	if (GetSize(c_const) > 32)
 		reject;
 
-	// Reuse/create new cell to drive the rewritten equation
+	// Reuse/create new cell to drive the folded expression
 	if (nusers(addsub1_y) != 2) {
 		cell = module->addCell(NEW_ID2_SUFFIX("asconst"), addsub1->type);
 		cell->attributes = addsub1->attributes;
diff --git a/tests/peepopt/addsub_c.ys b/tests/peepopt/addsub_c.ys
index 9a6a397cb..d8e09cc1e 100644
--- a/tests/peepopt/addsub_c.ys
+++ b/tests/peepopt/addsub_c.ys
@@ -178,7 +178,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] add;
 	assign add = 4'sd6 + a;
@@ -197,7 +197,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] sub;
 	assign sub = 4'sd6 - a;
@@ -216,7 +216,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] sub;
 	assign sub = 4'sd6 - a;
@@ -237,7 +237,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] add;
 	assign add = a + 4'sd6;
@@ -256,7 +256,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] add;
 	assign add = a + 4'sd6;
@@ -275,7 +275,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] sub;
 	assign sub = a - 4'sd6;
@@ -294,7 +294,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] sub;
 	assign sub = a - 4'sd6;
@@ -315,7 +315,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] add;
 	assign add = a + (-4'sd6);
@@ -334,7 +334,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] add;
 	assign add = a + (-4'sd6);
@@ -353,7 +353,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] sub;
 	assign sub = a - (-4'sd6);
@@ -372,7 +372,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] sub;
 	assign sub = a - (-4'sd6);
@@ -393,7 +393,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 	output signed [7:0] z,
 );
 	wire signed [7:0] add;
@@ -414,7 +414,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 	output signed [7:0] z,
 );
 	wire signed [7:0] add;
@@ -435,7 +435,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 	output signed [7:0] z,
 );
 	wire signed [7:0] sub;
@@ -456,7 +456,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 	output signed [7:0] z,
 );
 	wire signed [7:0] sub;