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yosys
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Merge branch 'YosysHQ:main' into main

This commit is contained in:
Akash Levy 2025-10-01 22:22:07 -07:00 committed by GitHub
parent a353716202 f7120e9c2a
commit aa16191b80
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3 changed files with 13 additions and 2 deletions
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2
Makefile
View File

@ -180,7 +180,7 @@ ifeq ($(OS), Haiku)
CXXFLAGS += -D_DEFAULT_SOURCE
endif
YOSYS_VER := 0.57+244
YOSYS_VER := 0.57+260
YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)

2
kernel/rtlil.h
View File

@ -411,7 +411,7 @@ struct RTLIL::IdString
}
bool empty() const {
return c_str()[0] == 0;
return index_ == 0;
}
void clear() {

11
techlibs/common/simlib.v
View File

@ -31,6 +31,14 @@
*
*/
// If using Verilator, define SIMLIB_VERILATOR_COMPAT
`ifdef SIMLIB_VERILATOR_COMPAT
/* verilator lint_save */
/* verilator lint_off DEFOVERRIDE */
`define SIMLIB_NOCONNECT
/* verilator lint_restore */
`endif
// --------------------------------------------------------
//* ver 2
//* title Bit-wise inverter
@ -3219,6 +3227,8 @@ endmodule
// --------------------------------------------------------
//* group wire
`ifndef SIMLIB_NOCONNECT
module \$connect (A, B);
parameter WIDTH = 0;
@ -3230,6 +3240,7 @@ tran connect[WIDTH-1:0] (A, B);
endmodule
`endif
// --------------------------------------------------------
//* group wire
module \$input_port (Y);