diff --git a/Makefile b/Makefile
index ec2096b83..4b37fb408 100644
--- a/Makefile
+++ b/Makefile
@@ -180,7 +180,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.57+244
+YOSYS_VER := 0.57+260
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index a9d2accdf..9fecfbb86 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -411,7 +411,7 @@ struct RTLIL::IdString
 	}
 
 	bool empty() const {
-		return c_str()[0] == 0;
+		return index_ == 0;
 	}
 
 	void clear() {
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 096df07b9..e0fb9fbfa 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -31,6 +31,14 @@
  *
  */
 
+// If using Verilator, define SIMLIB_VERILATOR_COMPAT
+`ifdef SIMLIB_VERILATOR_COMPAT
+ /* verilator lint_save */
+ /* verilator lint_off DEFOVERRIDE */
+ `define SIMLIB_NOCONNECT
+ /* verilator lint_restore */
+`endif
+
 // --------------------------------------------------------
 //* ver 2
 //* title Bit-wise inverter
@@ -3219,6 +3227,8 @@ endmodule
 
 // --------------------------------------------------------
 //* group wire
+`ifndef SIMLIB_NOCONNECT
+
 module \$connect (A, B);
 
 parameter WIDTH = 0;
@@ -3230,6 +3240,7 @@ tran connect[WIDTH-1:0] (A, B);
 
 endmodule
 
+`endif
 // --------------------------------------------------------
 //* group wire
 module \$input_port (Y);