From 0eb93c80e6048668cf2b63fad97ea572c2aa998e Mon Sep 17 00:00:00 2001
From: Ethan Sifferman <ethan@sifferman.dev>
Date: Wed, 24 Sep 2025 20:50:47 -0700
Subject: [PATCH 1/5] added ifndef SIMLIB_NOCONNECT

---
 techlibs/common/simlib.v | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 096df07b9..977b8bbf9 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -3219,6 +3219,8 @@ endmodule
 
 // --------------------------------------------------------
 //* group wire
+`ifndef SIMLIB_NOCONNECT
+
 module \$connect (A, B);
 
 parameter WIDTH = 0;
@@ -3230,6 +3232,7 @@ tran connect[WIDTH-1:0] (A, B);
 
 endmodule
 
+`endif
 // --------------------------------------------------------
 //* group wire
 module \$input_port (Y);

From 01eaaa4b902117f5819f076f7daaa0be0d48093d Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Wed, 1 Oct 2025 00:26:18 +0000
Subject: [PATCH 2/5] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 91f596258..54ad13d7c 100644
--- a/Makefile
+++ b/Makefile
@@ -164,7 +164,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.57+244
+YOSYS_VER := 0.57+254
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)

From d45223976ab4e9ed4b7d3d1973d3379d89d54e6c Mon Sep 17 00:00:00 2001
From: Robert O'Callahan <rocallahan@google.com>
Date: Wed, 1 Oct 2025 02:47:47 +0000
Subject: [PATCH 3/5] Optimize `IdString::empty()`

I actually saw this take 0.6% of the time in an `opt_clean` pass (under Module::check()).
Trivial issue, but the fix is also trivial and simple.
---
 kernel/rtlil.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 5271a3111..9f636c5a2 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -411,7 +411,7 @@ struct RTLIL::IdString
 	}
 
 	bool empty() const {
-		return c_str()[0] == 0;
+		return index_ == 0;
 	}
 
 	void clear() {

From d5beb65d306116147f104f750089c660255c1eb5 Mon Sep 17 00:00:00 2001
From: Ethan Sifferman <ethan@sifferman.dev>
Date: Wed, 1 Oct 2025 10:19:25 -0700
Subject: [PATCH 4/5] added SIMLIB_VERILATOR_COMPAT

---
 techlibs/common/simlib.v | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 977b8bbf9..e0fb9fbfa 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -31,6 +31,14 @@
  *
  */
 
+// If using Verilator, define SIMLIB_VERILATOR_COMPAT
+`ifdef SIMLIB_VERILATOR_COMPAT
+ /* verilator lint_save */
+ /* verilator lint_off DEFOVERRIDE */
+ `define SIMLIB_NOCONNECT
+ /* verilator lint_restore */
+`endif
+
 // --------------------------------------------------------
 //* ver 2
 //* title Bit-wise inverter

From f7120e9c2a922ef5e4520abd681816aa00c91bca Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Thu, 2 Oct 2025 00:22:09 +0000
Subject: [PATCH 5/5] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 54ad13d7c..ca589ff91 100644
--- a/Makefile
+++ b/Makefile
@@ -164,7 +164,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.57+254
+YOSYS_VER := 0.57+260
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)