mirror of https://github.com/YosysHQ/yosys.git
hierarchy: fix cache usage by caching false too
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07a615a283
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ae14b5e6a8
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@ -684,24 +684,30 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
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bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
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{
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if (cache.count(mod) == 0)
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for (auto c : mod->cells()) {
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RTLIL::Module *m = mod->design->module(c->type);
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if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
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return cache[mod] = true;
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}
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return cache[mod];
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auto it = cache.find(mod);
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if (it != cache.end())
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return it->second;
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cache[mod] = false;
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for (auto c : mod->cells()) {
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RTLIL::Module *m = mod->design->module(c->type);
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if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
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return cache[mod] = true;
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}
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return false;
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}
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bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
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{
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if (cache.count(mod) == 0)
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for (auto c : mod->cells()) {
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RTLIL::Module *m = mod->design->module(c->type);
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if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
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return cache[mod] = true;
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}
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return cache[mod];
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auto it = cache.find(mod);
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if (it != cache.end())
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return it->second;
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cache[mod] = false;
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for (auto c : mod->cells()) {
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RTLIL::Module *m = mod->design->module(c->type);
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if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
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return cache[mod] = true;
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}
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return false;
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}
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int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
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