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Merge pull request #6225 from YosysHQ/nella/abc-liberty-box-timing

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read_liberty: only mark cells as abc9 boxes when timing is imported
This commit is contained in:
nella
2026-09-21 16:08:27 +00:00
committed by GitHub
parent 563bda5023 d8d54fafd7
commit 968a634379
2 changed files with 21 additions and 35 deletions
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frontends/liberty/liberty.cc
+20 -22
View File
@@ -736,30 +736,28 @@ struct LibertyFrontend : public Frontend {
simple_comb_cell = false;
}
if (simple_comb_cell && has_outputs) {
if (simple_comb_cell && has_outputs && flag_unit_delay) {
module->set_bool_attribute(ID::abc9_box);
if (flag_unit_delay) {
for (auto wi : module->wires())
if (wi->port_input) {
for (auto wo : module->wires())
if (wo->port_output) {
RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2));
spec->setParam(ID::SRC_WIDTH, wi->width);
spec->setParam(ID::DST_WIDTH, wo->width);
spec->setParam(ID::T_FALL_MAX, 1000);
spec->setParam(ID::T_FALL_TYP, 1000);
spec->setParam(ID::T_FALL_MIN, 1000);
spec->setParam(ID::T_RISE_MAX, 1000);
spec->setParam(ID::T_RISE_TYP, 1000);
spec->setParam(ID::T_RISE_MIN, 1000);
spec->setParam(ID::SRC_DST_POL, false);
spec->setParam(ID::SRC_DST_PEN, false);
spec->setParam(ID::FULL, true);
spec->setPort(ID::EN, Const(1, 1));
spec->setPort(ID::SRC, wi);
spec->setPort(ID::DST, wo);
}
for (auto wi : module->wires())
if (wi->port_input) {
for (auto wo : module->wires())
if (wo->port_output) {
RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2));
spec->setParam(ID::SRC_WIDTH, wi->width);
spec->setParam(ID::DST_WIDTH, wo->width);
spec->setParam(ID::T_FALL_MAX, 1000);
spec->setParam(ID::T_FALL_TYP, 1000);
spec->setParam(ID::T_FALL_MIN, 1000);
spec->setParam(ID::T_RISE_MAX, 1000);
spec->setParam(ID::T_RISE_TYP, 1000);
spec->setParam(ID::T_RISE_MIN, 1000);
spec->setParam(ID::SRC_DST_POL, false);
spec->setParam(ID::SRC_DST_PEN, false);
spec->setParam(ID::FULL, true);
spec->setPort(ID::EN, Const(1, 1));
spec->setPort(ID::SRC, wi);
spec->setPort(ID::DST, wo);
}
}
}
tests/abc_new/librelane/generate_mk.py
+1 -13
View File
@@ -3,8 +3,6 @@
import sys
sys.path.append("../..")
import glob
import gen_tests_makefile
from construct_abc_script import ABCScriptCreator
@@ -24,10 +22,6 @@ config = {
strategies = ["AREA 0", "AREA 1", "AREA 2", "AREA 3",
"DELAY 0", "DELAY 1", "DELAY 2", "DELAY 3", "DELAY 4"]
skip = [
"read_liberty_lib.ys",
]
creator = ABCScriptCreator(config)
template = open("abc_librelane.ys.in").read()
for strategy in strategies:
@@ -36,10 +30,4 @@ for strategy in strategies:
with open(f"abc_librelane_{name}.ys", "w") as f:
f.write(template.replace("@STRATEGY@", strategy).replace("@SCRIPT@", script))
def create_tests():
for ys in sorted(glob.glob("*.ys")):
if ys in skip:
continue
gen_tests_makefile.generate_ys_test(ys)
gen_tests_makefile.generate_custom(create_tests)
gen_tests_makefile.generate(["--yosys-scripts"])