From d8d54fafd777157e9d34dfb88fd4183d65ec1617 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 21 Sep 2026 00:04:42 +0200 Subject: [PATCH] Mark cells as imported correctly. --- frontends/liberty/liberty.cc | 42 ++++++++++++-------------- tests/abc_new/librelane/generate_mk.py | 14 +-------- 2 files changed, 21 insertions(+), 35 deletions(-) diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 5d89c4f7d..eb793ba2d 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -736,30 +736,28 @@ struct LibertyFrontend : public Frontend { simple_comb_cell = false; } - if (simple_comb_cell && has_outputs) { + if (simple_comb_cell && has_outputs && flag_unit_delay) { module->set_bool_attribute(ID::abc9_box); - if (flag_unit_delay) { - for (auto wi : module->wires()) - if (wi->port_input) { - for (auto wo : module->wires()) - if (wo->port_output) { - RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2)); - spec->setParam(ID::SRC_WIDTH, wi->width); - spec->setParam(ID::DST_WIDTH, wo->width); - spec->setParam(ID::T_FALL_MAX, 1000); - spec->setParam(ID::T_FALL_TYP, 1000); - spec->setParam(ID::T_FALL_MIN, 1000); - spec->setParam(ID::T_RISE_MAX, 1000); - spec->setParam(ID::T_RISE_TYP, 1000); - spec->setParam(ID::T_RISE_MIN, 1000); - spec->setParam(ID::SRC_DST_POL, false); - spec->setParam(ID::SRC_DST_PEN, false); - spec->setParam(ID::FULL, true); - spec->setPort(ID::EN, Const(1, 1)); - spec->setPort(ID::SRC, wi); - spec->setPort(ID::DST, wo); - } + for (auto wi : module->wires()) + if (wi->port_input) { + for (auto wo : module->wires()) + if (wo->port_output) { + RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2)); + spec->setParam(ID::SRC_WIDTH, wi->width); + spec->setParam(ID::DST_WIDTH, wo->width); + spec->setParam(ID::T_FALL_MAX, 1000); + spec->setParam(ID::T_FALL_TYP, 1000); + spec->setParam(ID::T_FALL_MIN, 1000); + spec->setParam(ID::T_RISE_MAX, 1000); + spec->setParam(ID::T_RISE_TYP, 1000); + spec->setParam(ID::T_RISE_MIN, 1000); + spec->setParam(ID::SRC_DST_POL, false); + spec->setParam(ID::SRC_DST_PEN, false); + spec->setParam(ID::FULL, true); + spec->setPort(ID::EN, Const(1, 1)); + spec->setPort(ID::SRC, wi); + spec->setPort(ID::DST, wo); } } } diff --git a/tests/abc_new/librelane/generate_mk.py b/tests/abc_new/librelane/generate_mk.py index ec8984658..2ecbf1baf 100644 --- a/tests/abc_new/librelane/generate_mk.py +++ b/tests/abc_new/librelane/generate_mk.py @@ -3,8 +3,6 @@ import sys sys.path.append("../..") -import glob - import gen_tests_makefile from construct_abc_script import ABCScriptCreator @@ -24,10 +22,6 @@ config = { strategies = ["AREA 0", "AREA 1", "AREA 2", "AREA 3", "DELAY 0", "DELAY 1", "DELAY 2", "DELAY 3", "DELAY 4"] -skip = [ - "read_liberty_lib.ys", -] - creator = ABCScriptCreator(config) template = open("abc_librelane.ys.in").read() for strategy in strategies: @@ -36,10 +30,4 @@ for strategy in strategies: with open(f"abc_librelane_{name}.ys", "w") as f: f.write(template.replace("@STRATEGY@", strategy).replace("@SCRIPT@", script)) -def create_tests(): - for ys in sorted(glob.glob("*.ys")): - if ys in skip: - continue - gen_tests_makefile.generate_ys_test(ys) - -gen_tests_makefile.generate_custom(create_tests) +gen_tests_makefile.generate(["--yosys-scripts"])