More abc_new tests.

tests/techmap/abc_new_multibit_undriven.ys

@@ -0,0 +1,14 @@
+read_verilog <<EOT
+module top(input [3:0] a, output [3:0] y);
+	assign y = ~a;
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+logger -expect log "ABC: .*i/o = +4/ +4" 2
+logger -expect log "ABC: Warning: The network is combinational\." 1
+logger -expect log "ABC: Networks are equivalent\." 1
+logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver" 4
+logger -expect error "Found 4 problems in 'check -assert'" 1
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+check -assert

tests/techmap/abc_new_mux.ys

@@ -0,0 +1,65 @@
+design -reset
+read_verilog <<EOT
+module top(input a, input b, input sel, output y);
+	assign y = sel ? a : b;
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+logger -expect log "ABC: .*i/o = +3/ +1" 2
+logger -expect log "ABC: Warning: The network is combinational\." 1
+logger -expect log "ABC: Networks are equivalent\." 1
+logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
+logger -expect error "Found 1 problems in 'check -assert'" 1
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+check -assert
+
+design -reset
+read_verilog <<EOT
+module top(input [3:0] data, input [1:0] sel, output y);
+	assign y = data[sel];
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+logger -expect log "ABC: .*i/o = +6/ +1" 2
+logger -expect log "ABC: Warning: The network is combinational\." 1
+logger -expect log "ABC: Networks are equivalent\." 1
+logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
+logger -expect error "Found 1 problems in 'check -assert'" 1
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+check -assert
+
+design -reset
+read_verilog <<EOT
+module top(input a, input b, input c, input s1, input s2, output y);
+	wire temp;
+	assign temp = s1 ? a : b;
+	assign y = s2 ? temp : c;
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+logger -expect log "ABC: .*i/o = +5/ +1" 2
+logger -expect log "ABC: Warning: The network is combinational\." 1
+logger -expect log "ABC: Networks are equivalent\." 1
+logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
+logger -expect error "Found 1 problems in 'check -assert'" 1
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+check -assert
+
+design -reset
+read_verilog <<EOT
+module top(input [2:0] a, output [1:0] y);
+	assign y = a[2] ? 2'b11 : a[1] ? 2'b10 : a[0] ? 2'b01 : 2'b00;
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+logger -expect log "ABC: .*i/o = +3/ +2" 2
+logger -expect log "ABC: Warning: The network is combinational\." 1
+logger -expect log "ABC: Networks are equivalent\." 1
+logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 2
+logger -expect error "Found 2 problems in 'check -assert'" 1
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+check -assert

tests/techmap/abc_new_no_script.ys

@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input [3:0] a, input [3:0] b, output [3:0] y);
+	assign y = a & b;
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+logger -expect log "ABC: .*i/o = +8/ +4" 3
+logger -expect log "ABC: Warning: The network is combinational\." 1
+logger -expect error "Missing mapping \(no 'M' section\)" 1
+abc_new -liberty ../../examples/cmos/cmos_cells.lib

tests/techmap/abc_new_sc_undriven_wire.ys

@@ -0,0 +1,17 @@
+read_verilog <<EOT
+module top(input a, input b, output y);
+	assign y = a & b;
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+logger -expect warning "Feature 'abc_new' is experimental" 1
+logger -expect warning "Feature 'write_xaiger2' is experimental" 1
+logger -expect warning "Feature 'read_xaiger2' is experimental" 1
+logger -expect log "ABC: .*i/o = +2/ +1" 2
+logger -expect log "ABC: Warning: The network is combinational\." 1
+logger -expect log "ABC: Networks are equivalent\." 1
+logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
+logger -expect error "Found 1 problems in 'check -assert'" 1
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+check -assert

tests/techmap/abc_new_sc_verify_fails.ys

@@ -0,0 +1,17 @@
+read_verilog <<EOT
+module top(input a, input b, output y);
+	assign y = a & b;
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+logger -expect warning "Feature 'abc_new' is experimental" 1
+logger -expect warning "Feature 'write_xaiger2' is experimental" 1
+logger -expect warning "Feature 'read_xaiger2' is experimental" 1
+logger -expect log "ABC: .*i/o = +2/ +1" 2
+logger -expect log "ABC: Warning: The network is combinational\." 1
+logger -expect log "ABC: Networks are equivalent\." 1
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
+logger -expect error "Found 1 problems in 'check -assert'" 1
+check -assert

tests/techmap/abc_new_sequential.ys

@@ -0,0 +1,15 @@
+read_verilog <<EOT
+module top(input clk, input a, input b, output reg y);
+	always @(posedge clk) y <= a & b;
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+dfflibmap -liberty ../../examples/cmos/cmos_cells.lib
+logger -expect log "ABC: .*i/o = +4/ +3" 2
+logger -expect log "ABC: Warning: The network is combinational\." 1
+logger -expect log "ABC: Networks are equivalent\." 1
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+logger -expect error "Found 1 problems in 'check -assert'" 1
+check -assert
+