mirror of https://github.com/YosysHQ/yosys.git
11 lines
374 B
Plaintext
11 lines
374 B
Plaintext
read_verilog <<EOT
|
|
module top(input [3:0] a, input [3:0] b, output [3:0] y);
|
|
assign y = a & b;
|
|
endmodule
|
|
EOT
|
|
hierarchy -check -top top
|
|
proc; opt -fast
|
|
logger -expect log "ABC: .*i/o = +8/ +4" 3
|
|
logger -expect log "ABC: Warning: The network is combinational\." 1
|
|
logger -expect error "Missing mapping \(no 'M' section\)" 1
|
|
abc_new -liberty ../../examples/cmos/cmos_cells.lib |